1 | /*- |
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2 | * Copyright (c) 2004 John Baldwin <jhb@FreeBSD.org> |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * |
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14 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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16 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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17 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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18 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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20 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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21 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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22 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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23 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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24 | * SUCH DAMAGE. |
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25 | */ |
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26 | |
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27 | #include <sys/cdefs.h> |
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28 | #ifndef __rtems__ |
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29 | __FBSDID("$FreeBSD$"); |
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30 | #endif /* __rtems__ */ |
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31 | |
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32 | /* |
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33 | * The ELCR is a register that controls the trigger mode and polarity of |
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34 | * EISA and ISA interrupts. In FreeBSD 3.x and 4.x, the ELCR was only |
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35 | * consulted for determining the appropriate trigger mode of EISA |
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36 | * interrupts when using an APIC. However, it seems that almost all |
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37 | * systems that include PCI also include an ELCR that manages the ISA |
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38 | * IRQs 0 through 15. Thus, we check for the presence of an ELCR on |
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39 | * every machine by checking to see if the values found at bootup are |
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40 | * sane. Note that the polarity of ISA and EISA IRQs are linked to the |
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41 | * trigger mode. All edge triggered IRQs use active-hi polarity, and |
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42 | * all level triggered interrupts use active-lo polarity. |
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43 | * |
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44 | * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0 |
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45 | * controls IRQ 0, bit 1 controls IRQ 1, etc. If the bit is zero, the |
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46 | * associated IRQ is edge triggered. If the bit is one, the IRQ is |
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47 | * level triggered. |
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48 | */ |
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49 | |
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50 | #ifndef __rtems__ |
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51 | #include <sys/param.h> |
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52 | #include <sys/bus.h> |
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53 | #include <sys/systm.h> |
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54 | #include <machine/intr_machdep.h> |
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55 | #endif /* __rtems__ */ |
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56 | |
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57 | #ifdef __rtems__ |
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58 | #include <bsp.h> |
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59 | #include "i386_io.h" |
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60 | #include <errno.h> |
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61 | #include "elcr.h" |
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62 | #endif /* __rtems__ */ |
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63 | |
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64 | #define ELCR_PORT 0x4d0 |
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65 | #define ELCR_MASK(irq) (1 << (irq)) |
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66 | |
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67 | static int elcr_status; |
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68 | #ifdef __rtems__ |
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69 | static |
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70 | #endif /* __rtems__ */ |
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71 | int elcr_found; |
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72 | |
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73 | #ifdef __rtems__ |
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74 | #undef printf |
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75 | #define printf printk |
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76 | #define bootverbose 1 |
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77 | #define KASSERT(...) |
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78 | #endif /* __rtems__ */ |
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79 | |
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80 | /* |
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81 | * Check to see if we have what looks like a valid ELCR. We do this by |
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82 | * verifying that IRQs 0, 1, 2, and 13 are all edge triggered. |
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83 | */ |
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84 | int |
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85 | elcr_probe(void) |
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86 | { |
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87 | int i; |
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88 | |
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89 | elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8; |
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90 | if ((elcr_status & (ELCR_MASK(0) | ELCR_MASK(1) | ELCR_MASK(2) | |
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91 | ELCR_MASK(8) | ELCR_MASK(13))) != 0) |
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92 | return (ENXIO); |
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93 | if (bootverbose) { |
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94 | printf("ELCR Found. ISA IRQs programmed as:\n"); |
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95 | for (i = 0; i < 16; i++) |
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96 | printf(" %2d", i); |
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97 | printf("\n"); |
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98 | for (i = 0; i < 16; i++) |
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99 | if (elcr_status & ELCR_MASK(i)) |
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100 | printf(" L"); |
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101 | else |
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102 | printf(" E"); |
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103 | printf("\n"); |
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104 | } |
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105 | #ifndef __rtems__ |
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106 | if (resource_disabled("elcr", 0)) |
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107 | return (ENXIO); |
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108 | #endif /* __rtems__ */ |
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109 | elcr_found = 1; |
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110 | return (0); |
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111 | } |
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112 | |
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113 | /* |
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114 | * Returns 1 for level trigger, 0 for edge. |
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115 | */ |
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116 | enum intr_trigger |
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117 | elcr_read_trigger(u_int irq) |
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118 | { |
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119 | #ifdef __rtems__ |
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120 | if (!elcr_found) |
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121 | return INTR_TRIGGER_EDGE; |
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122 | #endif /* __rtems__ */ |
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123 | KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); |
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124 | KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); |
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125 | if (elcr_status & ELCR_MASK(irq)) |
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126 | return (INTR_TRIGGER_LEVEL); |
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127 | else |
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128 | return (INTR_TRIGGER_EDGE); |
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129 | } |
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130 | |
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131 | /* |
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132 | * Set the trigger mode for a specified IRQ. Mode of 0 means edge triggered, |
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133 | * and a mode of 1 means level triggered. |
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134 | */ |
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135 | void |
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136 | elcr_write_trigger(u_int irq, enum intr_trigger trigger) |
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137 | { |
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138 | int new_status; |
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139 | |
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140 | #ifdef __rtems__ |
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141 | if (!elcr_found) |
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142 | return; |
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143 | #endif /* __rtems__ */ |
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144 | KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); |
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145 | KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); |
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146 | if (trigger == INTR_TRIGGER_LEVEL) |
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147 | new_status = elcr_status | ELCR_MASK(irq); |
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148 | else |
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149 | new_status = elcr_status & ~ELCR_MASK(irq); |
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150 | if (new_status == elcr_status) |
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151 | return; |
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152 | elcr_status = new_status; |
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153 | if (irq >= 8) |
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154 | outb(ELCR_PORT + 1, elcr_status >> 8); |
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155 | else |
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156 | outb(ELCR_PORT, elcr_status & 0xff); |
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157 | } |
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158 | |
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159 | void |
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160 | elcr_resume(void) |
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161 | { |
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162 | #ifdef __rtems__ |
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163 | if (!elcr_found) |
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164 | return; |
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165 | #endif /* __rtems__ */ |
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166 | |
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167 | KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); |
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168 | outb(ELCR_PORT, elcr_status & 0xff); |
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169 | outb(ELCR_PORT + 1, elcr_status >> 8); |
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170 | } |
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