source: rtems/c/src/lib/libbsp/i386/shared/comm/uart.h @ dfddaf1

4.104.11
Last change on this file since dfddaf1 was dfddaf1, checked in by Ralf Corsepius <ralf.corsepius@…>, on Dec 10, 2009 at 1:55:22 PM

2009-12-10 Ralf Corsépius <ralf.corsepius@…>

  • shared/comm/uart.c, shared/comm/uart.h: Adjust prototypes.
  • Property mode set to 100644
File size: 5.8 KB
Line 
1/*
2 * This software is Copyright (C) 1998 by T.sqware - all rights limited
3 * It is provided in to the public domain "as is", can be freely modified
4 * as far as this copyight notice is kept unchanged, but does not imply
5 * an endorsement by T.sqware of the product in which it is included.
6 */
7
8#ifndef _BSPUART_H
9#define _BSPUART_H
10
11#ifdef __cplusplus
12extern "C" {
13#endif
14
15void BSP_uart_init(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits, int hwFlow);
16void BSP_uart_set_attributes(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits);
17void BSP_uart_set_baud(int uart, unsigned long baud);
18void BSP_uart_intr_ctrl(int uart, int cmd);
19void BSP_uart_throttle(int uart);
20void BSP_uart_unthrottle(int uart);
21int  BSP_uart_polled_status(int uart);
22void BSP_uart_polled_write(int uart, int val);
23int  BSP_uart_polled_read(int uart);
24void BSP_uart_termios_set(int uart, void *ttyp);
25int  BSP_uart_termios_read_com1(int uart);
26int  BSP_uart_termios_read_com2(int uart);
27int  BSP_uart_termios_write_com1(int minor, const char *buf, int len);
28int  BSP_uart_termios_write_com2(int minor, const char *buf, int len);
29void BSP_uart_termios_isr_com1();
30void BSP_uart_termios_isr_com2();
31void BSP_uart_dbgisr_com1(void);
32void BSP_uart_dbgisr_com2(void);
33extern int BSP_poll_char_via_serial(void);
34extern void BSP_output_char_via_serial(char val);
35extern int BSPConsolePort;
36extern int BSPBaseBaud;
37/*
38 * Command values for BSP_uart_intr_ctrl(),
39 * values are strange in order to catch errors
40 * with assert
41 */
42#define BSP_UART_INTR_CTRL_DISABLE  (0)
43#define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
44#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
45#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
46
47/* Return values for uart_polled_status() */
48#define BSP_UART_STATUS_ERROR    (-1) /* No character */
49#define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
50#define BSP_UART_STATUS_CHAR     (1)  /* Character present */
51#define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
52
53/* PC UART definitions */
54#define BSP_UART_COM1            (0)
55#define BSP_UART_COM2            (1)
56
57/*
58 * Base IO for UART
59 */
60
61#define COM1_BASE_IO    0x3F8
62#define COM2_BASE_IO    0x2F8
63
64/*
65 * Offsets from base
66 */
67
68/* DLAB 0 */
69#define RBR  (0)    /* Rx Buffer Register (read) */
70#define THR  (0)    /* Tx Buffer Register (write) */
71#define IER  (1)    /* Interrupt Enable Register */
72
73/* DLAB X */
74#define IIR  (2)    /* Interrupt Ident Register (read) */
75#define FCR  (2)    /* FIFO Control Register (write) */
76#define LCR  (3)    /* Line Control Register */
77#define MCR  (4)    /* Modem Control Register */
78#define LSR  (5)    /* Line Status Register */
79#define MSR  (6)    /* Modem Status  Register */
80#define SCR  (7)    /* Scratch register */
81
82/* DLAB 1 */
83#define DLL  (0)    /* Divisor Latch, LSB */
84#define DLM  (1)    /* Divisor Latch, MSB */
85#define AFR  (2)    /* Alternate Function register */
86
87/*
88 * Interrupt source definition via IIR
89 */
90#define MODEM_STATUS                            0
91#define NO_MORE_INTR                            1
92#define TRANSMITTER_HODING_REGISTER_EMPTY       2
93#define RECEIVER_DATA_AVAIL                     4
94#define RECEIVER_ERROR                          6
95#define CHARACTER_TIMEOUT_INDICATION            12
96
97/*
98 * Bits definition of IER
99 */
100#define RECEIVE_ENABLE          0x1
101#define TRANSMIT_ENABLE         0x2
102#define RECEIVER_LINE_ST_ENABLE 0x4
103#define MODEM_ENABLE            0x8
104#define INTERRUPT_DISABLE       0x0
105
106/*
107 * Bits definition of the Line Status Register (LSR)
108 */
109#define DR      0x01    /* Data Ready */
110#define OE      0x02    /* Overrun Error */
111#define PE      0x04    /* Parity Error */
112#define FE      0x08    /* Framing Error */
113#define BI      0x10    /* Break Interrupt */
114#define THRE    0x20    /* Transmitter Holding Register Empty */
115#define TEMT    0x40    /* Transmitter Empty */
116#define ERFIFO  0x80    /* Error receive Fifo */
117
118/*
119 * Bits definition of the MODEM Control Register (MCR)
120 */
121#define DTR     0x01    /* Data Terminal Ready */
122#define RTS     0x02    /* Request To Send */
123#define OUT_1   0x04    /* Output 1, (reserved on COMPAQ I/O Board) */
124#define OUT_2   0x08    /* Output 2, Enable Asynchronous Port Interrupts */
125#define LB      0x10    /* Enable Internal Loop Back */
126
127/*
128 * Bits definition of the Line Control Register (LCR)
129 */
130#define CHR_5_BITS 0
131#define CHR_6_BITS 1
132#define CHR_7_BITS 2
133#define CHR_8_BITS 3
134
135#define WL      0x03    /* Word length mask */
136#define STB     0x04    /* 1 Stop Bit, otherwise 2 Stop Bits */
137#define PEN     0x08    /* Parity Enabled */
138#define EPS     0x10    /* Even Parity Select, otherwise Odd */
139#define SP      0x20    /* Stick Parity */
140#define BCB     0x40    /* Break Control Bit */
141#define DLAB    0x80    /* Enable Divisor Latch Access */
142
143/*
144 * Bits definition of the MODEM Status Register (MSR)
145 */
146#define DCTS    0x01    /* Delta Clear To Send */
147#define DDSR    0x02    /* Delta Data Set Ready */
148#define TERI    0x04    /* Trailing Edge Ring Indicator */
149#define DDCD    0x08    /* Delta Carrier Detect Indicator */
150#define CTS     0x10    /* Clear To Send (when loop back is active) */
151#define DSR     0x20    /* Data Set Ready (when loop back is active) */
152#define RI      0x40    /* Ring Indicator (when loop back is active) */
153#define DCD     0x80    /* Data Carrier Detect (when loop back is active) */
154
155/*
156 * Bits definition of the FIFO Control Register : WD16C552 or NS16550
157 */
158
159#define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
160#define FIFO_EN     0x01    /* Enable the FIFO */
161#define XMIT_RESET  0x02    /* Transmit FIFO Reset */
162#define RCV_RESET   0x04    /* Receive FIFO Reset */
163#define FCR3        0x08    /* do not understand manual! */
164
165#define RECEIVE_FIFO_TRIGGER1   0x0  /* trigger recieve interrupt after 1 byte  */
166#define RECEIVE_FIFO_TRIGGER4   0x40 /* trigger recieve interrupt after 4 byte  */
167#define RECEIVE_FIFO_TRIGGER8   0x80 /* trigger recieve interrupt after 8 byte  */
168#define RECEIVE_FIFO_TRIGGER12  0xc0 /* trigger recieve interrupt after 12 byte */
169#define TRIG_LEVEL              0xc0 /* Mask for the trigger level              */
170
171#ifdef __cplusplus
172}
173#endif
174
175#endif /* _BSPUART_H */
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