source: rtems/c/src/lib/libbsp/i386/shared/comm/uart.h @ caeb33b2

4.104.114.84.95
Last change on this file since caeb33b2 was caeb33b2, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 3, 2001 at 5:56:32 PM

2001-07-03 Mike Seirs <mike@…>

  • comm/tty_drv.c, comm/uart.c, comm/uart.h: Adds the capability to use task driven serial I/O to ti386 BSPs. This patch leaves thex default I/O mode to be IRQ. If you want to use task I/O mode, then the tty_drv.c file needs to be modified. Basically, all you need to change is the data values of the termios callbacks structure. This callback structure is used in the tty1_open and tty2_open functions. The values you need to set are commented out in the source code.
  • Property mode set to 100644
File size: 5.8 KB
Line 
1
2
3/*
4 * This software is Copyright (C) 1998 by T.sqware - all rights limited
5 * It is provided in to the public domain "as is", can be freely modified
6 * as far as this copyight notice is kept unchanged, but does not imply
7 * an endorsement by T.sqware of the product in which it is included.
8 */
9
10#ifndef _BSPUART_H
11#define _BSPUART_H
12
13void BSP_uart_init(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits, int hwFlow);
14void BSP_uart_set_attributes(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits);
15void BSP_uart_set_baud(int uart, unsigned long baud);
16void BSP_uart_intr_ctrl(int uart, int cmd);
17void BSP_uart_throttle(int uart);
18void BSP_uart_unthrottle(int uart);
19int  BSP_uart_polled_status(int uart);
20void BSP_uart_polled_write(int uart, int val);
21int  BSP_uart_polled_read(int uart);
22void BSP_uart_termios_set(int uart, void *ttyp);
23int  BSP_uart_termios_read_com1(int uart);
24int  BSP_uart_termios_read_com2(int uart);
25int  BSP_uart_termios_write_com1(int minor, const char *buf, int len);
26int  BSP_uart_termios_write_com2(int minor, const char *buf, int len);
27void BSP_uart_termios_isr_com1();
28void BSP_uart_termios_isr_com2();
29void BSP_uart_dbgisr_com1(void);
30void BSP_uart_dbgisr_com2(void);
31extern unsigned BSP_poll_char_via_serial(void);
32extern void BSP_output_char_via_serial(int val);
33extern int BSPConsolePort;
34extern int BSPBaseBaud;
35/*
36 * Command values for BSP_uart_intr_ctrl(),
37 * values are strange in order to catch errors
38 * with assert
39 */
40#define BSP_UART_INTR_CTRL_DISABLE  (0)
41#define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
42#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
43#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
44
45/* Return values for uart_polled_status() */
46#define BSP_UART_STATUS_ERROR    (-1) /* No character */
47#define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
48#define BSP_UART_STATUS_CHAR     (1)  /* Character present */
49#define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
50
51/* PC UART definitions */
52#define BSP_UART_COM1            (0)
53#define BSP_UART_COM2            (1)
54
55/*
56 * Base IO for UART
57 */
58
59#define COM1_BASE_IO    0x3F8
60#define COM2_BASE_IO    0x2F8
61
62/*
63 * Offsets from base
64 */
65
66/* DLAB 0 */
67#define RBR  (0)    /* Rx Buffer Register (read) */
68#define THR  (0)    /* Tx Buffer Register (write) */
69#define IER  (1)    /* Interrupt Enable Register */
70
71/* DLAB X */
72#define IIR  (2)    /* Interrupt Ident Register (read) */
73#define FCR  (2)    /* FIFO Control Register (write) */
74#define LCR  (3)    /* Line Control Register */
75#define MCR  (4)    /* Modem Control Register */
76#define LSR  (5)    /* Line Status Register */
77#define MSR  (6)    /* Modem Status  Register */
78#define SCR  (7)    /* Scratch register */
79
80/* DLAB 1 */
81#define DLL  (0)    /* Divisor Latch, LSB */
82#define DLM  (1)    /* Divisor Latch, MSB */
83#define AFR  (2)    /* Alternate Function register */
84
85/*
86 * Interrupt source definition via IIR
87 */
88#define MODEM_STATUS                            0
89#define NO_MORE_INTR                            1
90#define TRANSMITTER_HODING_REGISTER_EMPTY       2
91#define RECEIVER_DATA_AVAIL                     4
92#define RECEIVER_ERROR                          6
93#define CHARACTER_TIMEOUT_INDICATION            12
94
95/*
96 * Bits definition of IER
97 */
98#define RECEIVE_ENABLE          0x1
99#define TRANSMIT_ENABLE         0x2
100#define RECEIVER_LINE_ST_ENABLE 0x4
101#define MODEM_ENABLE            0x8
102#define INTERRUPT_DISABLE       0x0
103
104/*
105 * Bits definition of the Line Status Register (LSR)
106 */
107#define DR      0x01    /* Data Ready */
108#define OE      0x02    /* Overrun Error */
109#define PE      0x04    /* Parity Error */
110#define FE      0x08    /* Framing Error */
111#define BI      0x10    /* Break Interrupt */
112#define THRE    0x20    /* Transmitter Holding Register Empty */
113#define TEMT    0x40    /* Transmitter Empty */
114#define ERFIFO  0x80    /* Error receive Fifo */
115
116/*
117 * Bits definition of the MODEM Control Register (MCR)
118 */
119#define DTR     0x01    /* Data Terminal Ready */
120#define RTS     0x02    /* Request To Send */
121#define OUT_1   0x04    /* Output 1, (reserved on COMPAQ I/O Board) */
122#define OUT_2   0x08    /* Output 2, Enable Asynchronous Port Interrupts */
123#define LB      0x10    /* Enable Internal Loop Back */
124
125/*
126 * Bits definition of the Line Control Register (LCR)
127 */
128#define CHR_5_BITS 0
129#define CHR_6_BITS 1
130#define CHR_7_BITS 2
131#define CHR_8_BITS 3
132
133#define WL      0x03    /* Word length mask */
134#define STB     0x04    /* 1 Stop Bit, otherwise 2 Stop Bits */
135#define PEN     0x08    /* Parity Enabled */
136#define EPS     0x10    /* Even Parity Select, otherwise Odd */
137#define SP      0x20    /* Stick Parity */
138#define BCB     0x40    /* Break Control Bit */
139#define DLAB    0x80    /* Enable Divisor Latch Access */
140
141/*
142 * Bits definition of the MODEM Status Register (MSR)
143 */
144#define DCTS    0x01    /* Delta Clear To Send */
145#define DDSR    0x02    /* Delta Data Set Ready */
146#define TERI    0x04    /* Trailing Edge Ring Indicator */
147#define DDCD    0x08    /* Delta Carrier Detect Indicator */
148#define CTS     0x10    /* Clear To Send (when loop back is active) */
149#define DSR     0x20    /* Data Set Ready (when loop back is active) */
150#define RI      0x40    /* Ring Indicator (when loop back is active) */
151#define DCD     0x80    /* Data Carrier Detect (when loop back is active) */
152
153/*
154 * Bits definition of the FIFO Control Register : WD16C552 or NS16550
155 */
156
157#define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
158#define FIFO_EN     0x01    /* Enable the FIFO */
159#define XMIT_RESET  0x02    /* Transmit FIFO Reset */
160#define RCV_RESET   0x04    /* Receive FIFO Reset */
161#define FCR3        0x08    /* do not understand manual! */
162
163#define RECEIVE_FIFO_TRIGGER1   0x0  /* trigger recieve interrupt after 1 byte  */
164#define RECEIVE_FIFO_TRIGGER4   0x40 /* trigger recieve interrupt after 4 byte  */
165#define RECEIVE_FIFO_TRIGGER8   0x80 /* trigger recieve interrupt after 8 byte  */
166#define RECEIVE_FIFO_TRIGGER12  0xc0 /* trigger recieve interrupt after 12 byte */
167#define TRIG_LEVEL              0xc0 /* Mask for the trigger level              */
168
169#endif /* _BSPUART_H */
170
171
172
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