source: rtems/c/src/lib/libbsp/i386/shared/comm/uart.h @ 5e1d6cb

Last change on this file since 5e1d6cb was 5e1d6cb, checked in by Ralf Corsepius <ralf.corsepius@…>, on Oct 8, 2003 at 3:37:53 PM

2003-10-08 Ralf Corsepius <corsepiu@…>

  • comm/uart.h: Add extern "C" guards.
  • pci/pcibios.h: Ditto.
  • Property mode set to 100644
File size: 5.8 KB
Line 
1
2
3/*
4 * This software is Copyright (C) 1998 by T.sqware - all rights limited
5 * It is provided in to the public domain "as is", can be freely modified
6 * as far as this copyight notice is kept unchanged, but does not imply
7 * an endorsement by T.sqware of the product in which it is included.
8 */
9
10#ifndef _BSPUART_H
11#define _BSPUART_H
12
13#ifdef __cplusplus
14extern "C" {
15#endif
16
17void BSP_uart_init(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits, int hwFlow);
18void BSP_uart_set_attributes(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits);
19void BSP_uart_set_baud(int uart, unsigned long baud);
20void BSP_uart_intr_ctrl(int uart, int cmd);
21void BSP_uart_throttle(int uart);
22void BSP_uart_unthrottle(int uart);
23int  BSP_uart_polled_status(int uart);
24void BSP_uart_polled_write(int uart, int val);
25int  BSP_uart_polled_read(int uart);
26void BSP_uart_termios_set(int uart, void *ttyp);
27int  BSP_uart_termios_read_com1(int uart);
28int  BSP_uart_termios_read_com2(int uart);
29int  BSP_uart_termios_write_com1(int minor, const char *buf, int len);
30int  BSP_uart_termios_write_com2(int minor, const char *buf, int len);
31void BSP_uart_termios_isr_com1();
32void BSP_uart_termios_isr_com2();
33void BSP_uart_dbgisr_com1(void);
34void BSP_uart_dbgisr_com2(void);
35extern unsigned BSP_poll_char_via_serial(void);
36extern void BSP_output_char_via_serial(int val);
37extern int BSPConsolePort;
38extern int BSPBaseBaud;
39/*
40 * Command values for BSP_uart_intr_ctrl(),
41 * values are strange in order to catch errors
42 * with assert
43 */
44#define BSP_UART_INTR_CTRL_DISABLE  (0)
45#define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
46#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
47#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
48
49/* Return values for uart_polled_status() */
50#define BSP_UART_STATUS_ERROR    (-1) /* No character */
51#define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
52#define BSP_UART_STATUS_CHAR     (1)  /* Character present */
53#define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
54
55/* PC UART definitions */
56#define BSP_UART_COM1            (0)
57#define BSP_UART_COM2            (1)
58
59/*
60 * Base IO for UART
61 */
62
63#define COM1_BASE_IO    0x3F8
64#define COM2_BASE_IO    0x2F8
65
66/*
67 * Offsets from base
68 */
69
70/* DLAB 0 */
71#define RBR  (0)    /* Rx Buffer Register (read) */
72#define THR  (0)    /* Tx Buffer Register (write) */
73#define IER  (1)    /* Interrupt Enable Register */
74
75/* DLAB X */
76#define IIR  (2)    /* Interrupt Ident Register (read) */
77#define FCR  (2)    /* FIFO Control Register (write) */
78#define LCR  (3)    /* Line Control Register */
79#define MCR  (4)    /* Modem Control Register */
80#define LSR  (5)    /* Line Status Register */
81#define MSR  (6)    /* Modem Status  Register */
82#define SCR  (7)    /* Scratch register */
83
84/* DLAB 1 */
85#define DLL  (0)    /* Divisor Latch, LSB */
86#define DLM  (1)    /* Divisor Latch, MSB */
87#define AFR  (2)    /* Alternate Function register */
88
89/*
90 * Interrupt source definition via IIR
91 */
92#define MODEM_STATUS                            0
93#define NO_MORE_INTR                            1
94#define TRANSMITTER_HODING_REGISTER_EMPTY       2
95#define RECEIVER_DATA_AVAIL                     4
96#define RECEIVER_ERROR                          6
97#define CHARACTER_TIMEOUT_INDICATION            12
98
99/*
100 * Bits definition of IER
101 */
102#define RECEIVE_ENABLE          0x1
103#define TRANSMIT_ENABLE         0x2
104#define RECEIVER_LINE_ST_ENABLE 0x4
105#define MODEM_ENABLE            0x8
106#define INTERRUPT_DISABLE       0x0
107
108/*
109 * Bits definition of the Line Status Register (LSR)
110 */
111#define DR      0x01    /* Data Ready */
112#define OE      0x02    /* Overrun Error */
113#define PE      0x04    /* Parity Error */
114#define FE      0x08    /* Framing Error */
115#define BI      0x10    /* Break Interrupt */
116#define THRE    0x20    /* Transmitter Holding Register Empty */
117#define TEMT    0x40    /* Transmitter Empty */
118#define ERFIFO  0x80    /* Error receive Fifo */
119
120/*
121 * Bits definition of the MODEM Control Register (MCR)
122 */
123#define DTR     0x01    /* Data Terminal Ready */
124#define RTS     0x02    /* Request To Send */
125#define OUT_1   0x04    /* Output 1, (reserved on COMPAQ I/O Board) */
126#define OUT_2   0x08    /* Output 2, Enable Asynchronous Port Interrupts */
127#define LB      0x10    /* Enable Internal Loop Back */
128
129/*
130 * Bits definition of the Line Control Register (LCR)
131 */
132#define CHR_5_BITS 0
133#define CHR_6_BITS 1
134#define CHR_7_BITS 2
135#define CHR_8_BITS 3
136
137#define WL      0x03    /* Word length mask */
138#define STB     0x04    /* 1 Stop Bit, otherwise 2 Stop Bits */
139#define PEN     0x08    /* Parity Enabled */
140#define EPS     0x10    /* Even Parity Select, otherwise Odd */
141#define SP      0x20    /* Stick Parity */
142#define BCB     0x40    /* Break Control Bit */
143#define DLAB    0x80    /* Enable Divisor Latch Access */
144
145/*
146 * Bits definition of the MODEM Status Register (MSR)
147 */
148#define DCTS    0x01    /* Delta Clear To Send */
149#define DDSR    0x02    /* Delta Data Set Ready */
150#define TERI    0x04    /* Trailing Edge Ring Indicator */
151#define DDCD    0x08    /* Delta Carrier Detect Indicator */
152#define CTS     0x10    /* Clear To Send (when loop back is active) */
153#define DSR     0x20    /* Data Set Ready (when loop back is active) */
154#define RI      0x40    /* Ring Indicator (when loop back is active) */
155#define DCD     0x80    /* Data Carrier Detect (when loop back is active) */
156
157/*
158 * Bits definition of the FIFO Control Register : WD16C552 or NS16550
159 */
160
161#define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
162#define FIFO_EN     0x01    /* Enable the FIFO */
163#define XMIT_RESET  0x02    /* Transmit FIFO Reset */
164#define RCV_RESET   0x04    /* Receive FIFO Reset */
165#define FCR3        0x08    /* do not understand manual! */
166
167#define RECEIVE_FIFO_TRIGGER1   0x0  /* trigger recieve interrupt after 1 byte  */
168#define RECEIVE_FIFO_TRIGGER4   0x40 /* trigger recieve interrupt after 4 byte  */
169#define RECEIVE_FIFO_TRIGGER8   0x80 /* trigger recieve interrupt after 8 byte  */
170#define RECEIVE_FIFO_TRIGGER12  0xc0 /* trigger recieve interrupt after 12 byte */
171#define TRIG_LEVEL              0xc0 /* Mask for the trigger level              */
172
173#ifdef __cplusplus
174}
175#endif
176
177
178#endif /* _BSPUART_H */
179
180
181
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