source: rtems/c/src/lib/libbsp/i386/pc386/console/uart_bus_pci.c @ 1503c1c3

Last change on this file since 1503c1c3 was 1503c1c3, checked in by Chris Johns <chrisj@…>, on May 23, 2016 at 5:24:34 AM

i386/pc386: Fix printk formatting warnings.

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File size: 14.2 KB
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1/*
2 * This file was brought over from FreeBSD for the PCI device table.
3 * The code for using the table is RTEMS specific is also under the
4 * FreeBSD license.
5 *
6 * COPYRIGHT (c) 1989-2012.
7 * On-Line Applications Research Corporation (OAR).
8 */
9
10/*-
11 * Copyright (c) 2006 Marcel Moolenaar
12 * Copyright (c) 2001 M. Warner Losh
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 *    notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 *    notice, this list of conditions and the following disclaimer in the
22 *    documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifdef __rtems__
37#include <stddef.h>
38#include <stdint.h>
39#include <i386_io.h>
40#else
41#include <sys/cdefs.h>
42__FBSDID("$FreeBSD$");
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/bus.h>
47#include <sys/conf.h>
48#include <sys/kernel.h>
49#include <sys/module.h>
50#include <machine/bus.h>
51#include <sys/rman.h>
52#include <machine/resource.h>
53
54#include <dev/pci/pcivar.h>
55
56#include <dev/uart/uart.h>
57#include <dev/uart/uart_bus.h>
58
59#endif
60
61#define DEFAULT_RCLK    1843200
62
63#ifndef __rtems__
64static int uart_pci_probe(device_t dev);
65
66static device_method_t uart_pci_methods[] = {
67        /* Device interface */
68        DEVMETHOD(device_probe,         uart_pci_probe),
69        DEVMETHOD(device_attach,        uart_bus_attach),
70        DEVMETHOD(device_detach,        uart_bus_detach),
71        DEVMETHOD(device_resume,        uart_bus_resume),
72        DEVMETHOD_END
73};
74
75static driver_t uart_pci_driver = {
76        uart_driver_name,
77        uart_pci_methods,
78        sizeof(struct uart_softc),
79};
80#endif
81
82struct pci_id {
83        uint16_t        vendor;
84        uint16_t        device;
85        uint16_t        subven;
86        uint16_t        subdev;
87        const char      *desc;
88        int             rid;
89        int             rclk;
90        int             regshft;
91};
92
93static const struct pci_id pci_ns8250_ids[] = {
94{ 0x1028, 0x0008, 0xffff, 0, "Dell Remote Access Card III", 0x14,
95        128 * DEFAULT_RCLK },
96{ 0x1028, 0x0012, 0xffff, 0, "Dell RAC 4 Daughter Card Virtual UART", 0x14,
97        128 * DEFAULT_RCLK },
98{ 0x1033, 0x0074, 0x1033, 0x8014, "NEC RCV56ACF 56k Voice Modem", 0x10 },
99{ 0x1033, 0x007d, 0x1033, 0x8012, "NEC RS232C", 0x10 },
100{ 0x103c, 0x1048, 0x103c, 0x1227, "HP Diva Serial [GSP] UART - Powerbar SP2",
101        0x10 },
102{ 0x103c, 0x1048, 0x103c, 0x1301, "HP Diva RMP3", 0x14 },
103{ 0x103c, 0x1290, 0xffff, 0, "HP Auxiliary Diva Serial Port", 0x18 },
104{ 0x103c, 0x3301, 0xffff, 0, "HP iLO serial port", 0x10 },
105{ 0x11c1, 0x0480, 0xffff, 0, "Agere Systems Venus Modem (V90, 56KFlex)", 0x14 },
106{ 0x115d, 0x0103, 0xffff, 0, "Xircom Cardbus Ethernet + 56k Modem", 0x10 },
107{ 0x1282, 0x6585, 0xffff, 0, "Davicom 56PDV PCI Modem", 0x10 },
108{ 0x12b9, 0x1008, 0xffff, 0, "3Com 56K FaxModem Model 5610", 0x10 },
109{ 0x131f, 0x1000, 0xffff, 0, "Siig CyberSerial (1-port) 16550", 0x18 },
110{ 0x131f, 0x1001, 0xffff, 0, "Siig CyberSerial (1-port) 16650", 0x18 },
111{ 0x131f, 0x1002, 0xffff, 0, "Siig CyberSerial (1-port) 16850", 0x18 },
112{ 0x131f, 0x2000, 0xffff, 0, "Siig CyberSerial (1-port) 16550", 0x10 },
113{ 0x131f, 0x2001, 0xffff, 0, "Siig CyberSerial (1-port) 16650", 0x10 },
114{ 0x131f, 0x2002, 0xffff, 0, "Siig CyberSerial (1-port) 16850", 0x10 },
115{ 0x135c, 0x0190, 0xffff, 0, "Quatech SSCLP-100", 0x18 },
116{ 0x135c, 0x01c0, 0xffff, 0, "Quatech SSCLP-200/300", 0x18 },
117{ 0x135e, 0x7101, 0xffff, 0, "Sealevel Systems Single Port RS-232/422/485/530",
118        0x18 },
119{ 0x1407, 0x0110, 0xffff, 0, "Lava Computer mfg DSerial-PCI Port A", 0x10 },
120{ 0x1407, 0x0111, 0xffff, 0, "Lava Computer mfg DSerial-PCI Port B", 0x10 },
121{ 0x1407, 0x0510, 0xffff, 0, "Lava SP Serial 550 PCI", 0x10 },
122{ 0x1409, 0x7168, 0x1409, 0x4025, "Timedia Technology Serial Port", 0x10,
123        8 * DEFAULT_RCLK },
124{ 0x1409, 0x7168, 0x1409, 0x4027, "Timedia Technology Serial Port", 0x10,
125        8 * DEFAULT_RCLK },
126{ 0x1409, 0x7168, 0x1409, 0x4028, "Timedia Technology Serial Port", 0x10,
127        8 * DEFAULT_RCLK },
128{ 0x1409, 0x7168, 0x1409, 0x5025, "Timedia Technology Serial Port", 0x10,
129        8 * DEFAULT_RCLK },
130{ 0x1409, 0x7168, 0x1409, 0x5027, "Timedia Technology Serial Port", 0x10,
131        8 * DEFAULT_RCLK },
132{ 0x1415, 0x950b, 0xffff, 0, "Oxford Semiconductor OXCB950 Cardbus 16950 UART",
133        0x10, 16384000 },
134{ 0x1415, 0xc120, 0xffff, 0, "Oxford Semiconductor OXPCIe952 PCIe 16950 UART",
135        0x10 },
136{ 0x14e4, 0x4344, 0xffff, 0, "Sony Ericsson GC89 PC Card", 0x10},
137{ 0x151f, 0x0000, 0xffff, 0, "TOPIC Semiconductor TP560 56k modem", 0x10 },
138{ 0x1fd4, 0x1999, 0x1fd4, 0x0001, "Sunix SER5xxxx Serial Port", 0x10,
139        8 * DEFAULT_RCLK },
140{ 0x8086, 0x0f0a, 0xffff, 0, "Intel ValleyView LPIO1 HSUART#1", 0x10,
141        24 * DEFAULT_RCLK, 2 },
142{ 0x8086, 0x0f0c, 0xffff, 0, "Intel ValleyView LPIO1 HSUART#2", 0x10,
143        24 * DEFAULT_RCLK, 2 },
144{ 0x8086, 0x1c3d, 0xffff, 0, "Intel AMT - KT Controller", 0x10 },
145{ 0x8086, 0x1d3d, 0xffff, 0, "Intel C600/X79 Series Chipset KT Controller", 0x10 },
146{ 0x8086, 0x2a07, 0xffff, 0, "Intel AMT - PM965/GM965 KT Controller", 0x10 },
147{ 0x8086, 0x2a47, 0xffff, 0, "Mobile 4 Series Chipset KT Controller", 0x10 },
148{ 0x8086, 0x2e17, 0xffff, 0, "4 Series Chipset Serial KT Controller", 0x10 },
149{ 0x8086, 0x3b67, 0xffff, 0, "5 Series/3400 Series Chipset KT Controller",
150        0x10 },
151{ 0x8086, 0x8811, 0xffff, 0, "Intel EG20T Serial Port 0", 0x10 },
152{ 0x8086, 0x8812, 0xffff, 0, "Intel EG20T Serial Port 1", 0x10 },
153{ 0x8086, 0x8813, 0xffff, 0, "Intel EG20T Serial Port 2", 0x10 },
154{ 0x8086, 0x8814, 0xffff, 0, "Intel EG20T Serial Port 3", 0x10 },
155{ 0x8086, 0x8c3d, 0xffff, 0, "Intel Lynx Point KT Controller", 0x10 },
156{ 0x8086, 0x8cbd, 0xffff, 0, "Intel Wildcat Point KT Controller", 0x10 },
157{ 0x8086, 0x9c3d, 0xffff, 0, "Intel Lynx Point-LP HECI KT", 0x10 },
158{ 0x9710, 0x9820, 0x1000, 1, "NetMos NM9820 Serial Port", 0x10 },
159{ 0x9710, 0x9835, 0x1000, 1, "NetMos NM9835 Serial Port", 0x10 },
160{ 0x9710, 0x9865, 0xa000, 0x1000, "NetMos NM9865 Serial Port", 0x10 },
161{ 0x9710, 0x9900, 0xa000, 0x1000,
162        "MosChip MCS9900 PCIe to Peripheral Controller", 0x10 },
163{ 0x9710, 0x9901, 0xa000, 0x1000,
164        "MosChip MCS9901 PCIe to Peripheral Controller", 0x10 },
165{ 0x9710, 0x9904, 0xa000, 0x1000,
166        "MosChip MCS9904 PCIe to Peripheral Controller", 0x10 },
167{ 0x9710, 0x9922, 0xa000, 0x1000,
168        "MosChip MCS9922 PCIe to Peripheral Controller", 0x10 },
169{ 0xdeaf, 0x9051, 0xffff, 0, "Middle Digital PC Weasel Serial Port", 0x10 },
170{ 0xffff, 0, 0xffff, 0, NULL, 0, 0}
171};
172
173#ifndef __rtems__
174const static struct pci_id *
175uart_pci_match(device_t dev, const struct pci_id *id)
176{
177        uint16_t device, subdev, subven, vendor;
178
179        vendor = pci_get_vendor(dev);
180        device = pci_get_device(dev);
181        while (id->vendor != 0xffff &&
182            (id->vendor != vendor || id->device != device))
183                id++;
184        if (id->vendor == 0xffff)
185                return (NULL);
186        if (id->subven == 0xffff)
187                return (id);
188        subven = pci_get_subvendor(dev);
189        subdev = pci_get_subdevice(dev);
190        while (id->vendor == vendor && id->device == device &&
191            (id->subven != subven || id->subdev != subdev))
192                id++;
193        return ((id->vendor == vendor && id->device == device) ? id : NULL);
194}
195
196static int
197uart_pci_probe(device_t dev)
198{
199        struct uart_softc *sc;
200        const struct pci_id *id;
201        int result;
202
203        sc = device_get_softc(dev);
204
205        id = uart_pci_match(dev, pci_ns8250_ids);
206        if (id != NULL) {
207                sc->sc_class = &uart_ns8250_class;
208                goto match;
209        }
210        /* Add checks for non-ns8250 IDs here. */
211        return (ENXIO);
212
213 match:
214        result = uart_bus_probe(dev, id->regshft, id->rclk, id->rid, 0);
215        /* Bail out on error. */
216        if (result > 0)
217                return (result);
218        /* Set/override the device description. */
219        if (id->desc)
220                device_set_desc(dev, id->desc);
221        return (result);
222}
223
224DRIVER_MODULE(uart, pci, uart_pci_driver, uart_devclass, NULL, NULL);
225#endif
226
227#ifdef __rtems__
228
229#include <bsp.h>
230#include <bsp/bspimpl.h>
231
232#include <stdio.h>
233#include <stdlib.h>
234
235#include <libchip/serial.h>
236#include <libchip/ns16550.h>
237#include <rtems/bspIo.h>
238#include <rtems/pci.h>
239#include "../../../shared/console_private.h"
240
241#define MAX_BOARDS 4
242
243/*
244 * Information saved from PCI scan
245 */
246typedef struct {
247  bool        found;
248  const char* desc;
249  uint32_t    base;
250  uint8_t     irq;
251  uint8_t     bus;
252  uint8_t     slot;
253  int         ports;
254  uint32_t    clock;
255} port_instance_conf_t;
256
257/*
258 *  Memory Mapped Register Access Routines
259 */
260
261#define UART_PCI_IO (0)
262
263static uint8_t pci_ns16550_mem_get_register(uint32_t addr, uint8_t i)
264{
265  uint8_t          val = 0;
266  volatile uint32_t *reg = (volatile uint32_t *)(addr + (i*4));
267  val = *reg;
268  if (UART_PCI_IO)
269    printk( "RD(%p -> 0x%02x) ", reg, val );
270  return val;
271}
272
273static void pci_ns16550_mem_set_register(uint32_t addr, uint8_t i, uint8_t val)
274{
275  volatile uint32_t *reg = (volatile uint32_t *)(addr + (i*4));
276  if (UART_PCI_IO)
277    printk( "WR(%p <- 0x%02x) ", reg, val );
278  *reg = val;
279}
280
281/*
282 *  IO Register Access Routines
283 */
284static uint8_t pci_ns16550_io_get_register(uint32_t addr, uint8_t i)
285{
286  uint8_t val = rtems_inb(addr + i);
287  if (UART_PCI_IO)
288    printk( "RD(%p -> 0x%02x) ", (void*) addr + i, val );
289  return val;
290}
291
292static void pci_ns16550_io_set_register(uint32_t addr, uint8_t i, uint8_t val)
293{
294  if (UART_PCI_IO)
295    printk( "WR(%p <- 0x%02x) ", (void*) addr + i, val );
296  rtems_outb(addr + i, val);
297}
298
299void pci_uart_probe(void)
300{
301  port_instance_conf_t  conf[MAX_BOARDS];
302  int                   boards = 0;
303  int                   b = 0;
304  console_tbl          *ports;
305  console_tbl          *port_p;
306  int                   bus;
307  int                   dev;
308  int                   fun;
309  int                   status;
310  int                   instance;
311  int                   i;
312  int                   total_ports = 0;
313
314  for ( b=0 ; b<MAX_BOARDS ; b++ ) {
315    conf[b].found = false;
316  }
317
318  /*
319   *  Scan for Serial port boards
320   */
321  for ( instance=0 ; instance < MAX_BOARDS ; instance++ ) {
322
323    for ( i=0 ; pci_ns8250_ids[i].vendor != 0xffff ; i++ ) {
324      if ( pci_ns8250_ids[i].vendor == 0xffff ) {
325        break;
326      }
327/*
328      printk("Looking for 0x%04x:0x%04x\n",
329        pci_ns8250_ids[i].vendor,
330        pci_ns8250_ids[i].device);
331*/
332      status = pci_find_device(
333        pci_ns8250_ids[i].vendor,
334        pci_ns8250_ids[i].device,
335        instance,
336        &bus,
337        &dev,
338        &fun
339      );
340      if ( status == PCIB_ERR_SUCCESS ) {
341        uint8_t  irq;
342        uint32_t base;
343        bool io;
344
345        pci_read_config_dword( bus, dev, fun, PCI_BASE_ADDRESS_0, &base );
346
347        /*
348         * Reject memory mapped 64-bit boards. We need 2 BAR registers and the
349         * driver's base field is only 32-bits any way.
350         */
351        io = (base & 1) == 1;
352        if (io || (!io && (((base >> 1) & 3) != 2))) {
353          boards++;
354          conf[instance].found = true;
355          conf[instance].desc = pci_ns8250_ids[i].desc;
356          conf[instance].clock =  pci_ns8250_ids[i].rclk;
357          conf[instance].ports = 1;
358          total_ports += conf[instance].ports;
359
360          pci_read_config_byte( bus, dev, fun, PCI_INTERRUPT_LINE, &irq );
361
362          conf[instance].irq  = irq;
363          conf[instance].base = base;
364        }
365      }
366    }
367  }
368
369  /*
370   *  Now allocate array of device structures and fill them in
371   */
372  if (boards) {
373    int device_instance;
374
375    ports = calloc( total_ports, sizeof( console_tbl ) );
376    if (ports != NULL) {
377      port_p = ports;
378      device_instance = 1;
379      for (b = 0; b < MAX_BOARDS; b++) {
380        uint32_t base = 0;
381        bool io;
382        const char* locatable = "";
383        const char* prefectable = locatable;
384        char name[32];
385        if ( conf[b].found == false )
386          continue;
387        sprintf( name, "/dev/pcicom%d", device_instance++ );
388        port_p->sDeviceName   = strdup( name );
389        port_p->deviceType    = SERIAL_NS16550;
390        if ( conf[b].irq <= 15 ) {
391          port_p->pDeviceFns    = &ns16550_fns;
392        } else {
393          printk(
394            "%s IRQ=%d >= 16 requires APIC support, using polling\n",
395            name,
396            conf[b].irq
397          );
398          port_p->pDeviceFns    = &ns16550_fns_polled;
399        }
400
401        /*
402         * PCI BAR (http://wiki.osdev.org/PCI#Base_Address_Registers):
403         *
404         *  Bit 0: 0 = memory, 1 = IO
405         *
406         * Memory:
407         *  Bit 2-1  : 0 = any 32bit address,
408         *             1 = < 1M
409         *             2 = any 64bit address
410         *  Bit 3    : 0 = no, 1 = yes
411         *  Bit 31-4 : base address (16-byte aligned)
412         *
413         * IO:
414         *  Bit 1    : reserved
415         *  Bit 31-2 : base address (4-byte aligned)
416         */
417
418        io = (conf[b].base & 1) == 1;
419
420        if (io) {
421          base = conf[b].base & 0xfffffffc;
422        } else {
423          int loc = (conf[b].base >> 1) & 3;
424          if (loc == 0) {
425            base = conf[b].base & 0xfffffff0;
426            locatable = ",A32";
427          } else if (loc == 1) {
428            base = conf[b].base & 0x0000fff0;
429            locatable = ",A16";
430          }
431          prefectable = (conf[b].base & (1 << 3)) == 0 ? ",no-prefech" : ",prefetch";
432        }
433
434        port_p->deviceProbe   = NULL;
435        port_p->pDeviceFlow   = NULL;
436        port_p->ulMargin      = 16;
437        port_p->ulHysteresis  = 8;
438        port_p->pDeviceParams = (void *) 9600;
439        port_p->ulCtrlPort1   = base;
440        port_p->ulCtrlPort2   = 0;                   /* NA */
441        port_p->ulDataPort    = 0;                   /* NA */
442        if (io) {
443          port_p->getRegister = pci_ns16550_io_get_register;
444          port_p->setRegister = pci_ns16550_io_set_register;
445        } else {
446          port_p->getRegister = pci_ns16550_mem_get_register;
447          port_p->setRegister = pci_ns16550_mem_set_register;
448        }
449        port_p->getData       = NULL;                /* NA */
450        port_p->setData       = NULL;                /* NA */
451        port_p->ulClock       = conf[b].clock;
452        port_p->ulIntVector   = conf[b].irq;
453
454
455        printk(
456          "%s:%d:%s,%s:0x%lx%s%s,irq:%d,clk:%lu\n", /*  */
457          name, b, conf[b].desc,
458          io ? "io" : "mem", base, locatable, prefectable,
459          conf[b].irq, conf[b].clock
460        );
461
462
463        port_p++;
464      }    /* end boards */
465
466      /*
467       *  Register the devices
468       */
469      console_register_devices( ports, total_ports );
470
471      /*
472       *  Do not free the ports memory, the console hold this memory for-ever.
473       */
474    }
475  }
476}
477#endif
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