1 | /* |
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2 | * FB driver for Cirrus GD5446 graphic hardware. |
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3 | * Tested to be compatible with QEMU GD5446 emulation but not on real HW. |
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4 | * |
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5 | * Copyright (c) 2012 - Alexandru-Sever Horin (alex.sever.h@gmail.com). |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.org/license/LICENSE. |
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10 | * |
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11 | * The code is based on next information sources: |
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12 | * - CL-GD5446 Technical Reference Manual, 1996, Second Edition |
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13 | * - RTEMS fb_vga.c - Rosimildo da Silva ( rdasilva@connecttel.com ) |
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14 | * - Cirrus xf86 driver - used as VGA hardware setup sequence documentation |
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15 | */ |
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16 | |
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17 | #include <stdlib.h> |
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18 | #include <stdio.h> |
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19 | #include <errno.h> |
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20 | #include <sys/types.h> |
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21 | #include <pthread.h> |
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22 | |
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23 | #include <bsp.h> |
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24 | #include <bsp/irq.h> |
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25 | #include <rtems/libio.h> |
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26 | #include <rtems/pci.h> |
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27 | |
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28 | #include <rtems/fb.h> |
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29 | #include <rtems/framebuffer.h> |
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30 | #include <rtems/score/atomic.h> |
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31 | |
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32 | /* flag to limit driver to protect against multiple opens */ |
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33 | static Atomic_Flag driver_mutex; |
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34 | |
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35 | /* screen information for the VGA driver |
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36 | * standard structures |
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37 | */ |
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38 | static struct fb_var_screeninfo fb_var; |
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39 | static struct fb_fix_screeninfo fb_fix; |
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40 | |
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41 | #define CIRRUS_VENDOR_ID 0x1013 |
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42 | #define CIRRUS_GD5446_DEVICE_ID 0x00b8 |
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43 | |
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44 | typedef struct _DisplayModeRec { |
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45 | struct _DisplayModeRec *prev; |
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46 | struct _DisplayModeRec *next; |
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47 | char *name; /* identifier for the mode */ |
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48 | int type; |
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49 | |
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50 | /* These are the values that the user sees/provides */ |
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51 | int Clock; /* pixel clock freq (kHz) */ |
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52 | int HDisplay; /* horizontal timing */ |
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53 | int HSyncStart; |
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54 | int HSyncEnd; |
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55 | int HTotal; |
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56 | int HSkew; |
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57 | int VDisplay; /* vertical timing */ |
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58 | int VSyncStart; |
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59 | int VSyncEnd; |
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60 | int VTotal; |
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61 | int VScan; |
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62 | int Flags; |
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63 | |
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64 | /* These are the values the hardware uses */ |
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65 | int ClockIndex; |
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66 | int SynthClock; /* Actual clock freq to |
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67 | * be programmed (kHz) */ |
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68 | int CrtcHDisplay; |
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69 | int CrtcHBlankStart; |
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70 | int CrtcHSyncStart; |
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71 | int CrtcHSyncEnd; |
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72 | int CrtcHBlankEnd; |
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73 | int CrtcHTotal; |
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74 | int CrtcHSkew; |
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75 | int CrtcVDisplay; |
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76 | int CrtcVBlankStart; |
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77 | int CrtcVSyncStart; |
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78 | int CrtcVSyncEnd; |
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79 | int CrtcVBlankEnd; |
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80 | int CrtcVTotal; |
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81 | int CrtcHAdjusted; |
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82 | int CrtcVAdjusted; |
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83 | int PrivSize; |
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84 | int32_t *Private; |
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85 | int PrivFlags; |
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86 | |
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87 | float HSync, VRefresh; |
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88 | } DisplayModeRec, *DisplayModePtr; |
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89 | |
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90 | static DisplayModeRec available_modes[] = { |
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91 | { |
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92 | .Clock = 31500 , |
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93 | .HDisplay = 640 , |
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94 | .HSyncStart = 664 , |
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95 | .HSyncEnd = 704 , |
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96 | .HTotal = 832 , |
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97 | .HSkew = 0 , |
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98 | .VDisplay = 480 , /* vertical timing */ |
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99 | .VSyncStart = 489 , |
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100 | .VSyncEnd = 491 , |
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101 | .VTotal = 520 , |
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102 | .VScan = 0, |
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103 | .Flags = 0 |
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104 | }, |
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105 | { |
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106 | .Clock = 40000 , |
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107 | .HDisplay = 800 , |
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108 | .HSyncStart = 840 , |
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109 | .HSyncEnd = 968 , |
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110 | .HTotal = 1056 , |
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111 | .HSkew = 0 , |
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112 | .VDisplay = 600 , /* vertical timing */ |
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113 | .VSyncStart = 601 , |
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114 | .VSyncEnd = 605 , |
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115 | .VTotal = 628 , |
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116 | .VScan = 0, |
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117 | .Flags = 0 |
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118 | }, |
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119 | }; |
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120 | static DisplayModePtr active_mode; |
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121 | |
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122 | /* The display mode used for the board hardcoded in the following define |
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123 | * Index in above structure |
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124 | */ |
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125 | #define CIRRUS_DISPLAY_MODE 0 |
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126 | |
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127 | /* The display bytes per pixel used for the board hardcoded in the following define |
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128 | * Index in above structure |
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129 | */ |
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130 | #define CIRRUS_DEFAULT_BPP 24 |
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131 | |
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132 | /* cirrus board information */ |
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133 | struct cirrus_board_str{ |
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134 | int pci_bus; |
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135 | int pci_device; |
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136 | int pci_function; |
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137 | void *reg_base; |
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138 | }; |
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139 | |
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140 | static struct cirrus_board_str cirrus_board_info; |
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141 | |
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142 | /* |
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143 | * get information from the board |
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144 | */ |
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145 | static int |
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146 | cirrus_pci_read( struct cirrus_board_str *cirrus_board, uint32_t *mem_base, uint32_t *cirrus_register_base) |
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147 | { |
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148 | int r; |
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149 | |
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150 | r = pci_read_config_dword( |
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151 | cirrus_board->pci_bus, cirrus_board->pci_device, cirrus_board->pci_function, |
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152 | PCI_BASE_ADDRESS_0, mem_base); |
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153 | if( r != PCIB_ERR_SUCCESS) |
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154 | return RTEMS_UNSATISFIED; |
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155 | |
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156 | r = pci_read_config_dword( |
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157 | cirrus_board->pci_bus, cirrus_board->pci_device, cirrus_board->pci_function, |
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158 | PCI_BASE_ADDRESS_1, cirrus_register_base); |
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159 | if( r != PCIB_ERR_SUCCESS) |
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160 | return RTEMS_UNSATISFIED; |
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161 | |
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162 | *mem_base &= PCI_BASE_ADDRESS_MEM_MASK; |
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163 | *cirrus_register_base &= PCI_BASE_ADDRESS_MEM_MASK; |
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164 | |
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165 | return RTEMS_SUCCESSFUL; |
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166 | } |
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167 | |
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168 | static inline int |
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169 | fb_cirrus_read_config_dword( |
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170 | struct cirrus_board_str *fbst, |
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171 | unsigned char where, |
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172 | uint32_t *pval) |
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173 | { |
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174 | return pci_read_config_dword( |
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175 | fbst->pci_bus, fbst->pci_device, fbst->pci_function, |
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176 | where, pval); |
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177 | } |
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178 | |
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179 | static inline int |
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180 | fb_cirrus_write_config_dword( |
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181 | struct cirrus_board_str *fbst, |
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182 | unsigned char where, |
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183 | uint32_t val) |
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184 | { |
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185 | return pci_write_config_dword( |
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186 | fbst->pci_bus, fbst->pci_device, fbst->pci_function, |
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187 | where, val); |
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188 | } |
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189 | |
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190 | static inline void |
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191 | fb_cirrus_write_reg8 ( |
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192 | const struct cirrus_board_str *fbst, |
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193 | unsigned int reg, |
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194 | unsigned int val) |
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195 | { |
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196 | *(volatile uint8_t*)((char *)fbst->reg_base + reg) = val; |
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197 | } |
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198 | |
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199 | static inline unsigned int |
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200 | fb_cirrus_read_reg8 ( |
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201 | const struct cirrus_board_str *fbst, |
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202 | unsigned int reg) |
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203 | { |
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204 | return *(volatile uint8_t*)((char *)fbst->reg_base + reg); |
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205 | } |
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206 | |
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207 | #define SEQ_INDEX 0x04 |
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208 | #define SEQ_DATA 0x05 |
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209 | |
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210 | static inline void |
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211 | fb_cirrus_write_seq_reg ( |
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212 | const struct cirrus_board_str *fbst, |
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213 | unsigned int reg, |
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214 | unsigned int val) |
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215 | { |
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216 | fb_cirrus_write_reg8(fbst, SEQ_INDEX, reg); |
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217 | fb_cirrus_write_reg8(fbst, SEQ_DATA, val); |
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218 | } |
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219 | |
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220 | static inline unsigned int |
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221 | fb_cirrus_read_seq_reg ( |
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222 | const struct cirrus_board_str *fbst, |
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223 | unsigned int reg) |
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224 | { |
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225 | fb_cirrus_write_reg8(fbst, SEQ_INDEX, reg); |
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226 | return fb_cirrus_read_reg8(fbst, SEQ_DATA); |
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227 | } |
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228 | |
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229 | #define CRT_INDEX 0x14 |
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230 | #define CRT_DATA 0x15 |
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231 | |
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232 | static inline void |
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233 | fb_cirrus_write_crt_reg ( |
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234 | const struct cirrus_board_str *fbst, |
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235 | unsigned int reg, |
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236 | unsigned int val) |
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237 | { |
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238 | fb_cirrus_write_reg8(fbst, CRT_INDEX, reg); |
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239 | fb_cirrus_write_reg8(fbst, CRT_DATA, val); |
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240 | } |
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241 | |
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242 | static inline unsigned int |
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243 | fb_cirrus_read_crt_reg ( |
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244 | const struct cirrus_board_str *fbst, |
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245 | unsigned int reg) |
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246 | { |
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247 | fb_cirrus_write_reg8(fbst, CRT_INDEX, reg); |
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248 | return fb_cirrus_read_reg8(fbst, CRT_DATA); |
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249 | } |
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250 | |
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251 | #define GDC_INDEX 0x0E |
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252 | #define GDC_DATA 0x0F |
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253 | |
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254 | static inline void |
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255 | fb_cirrus_write_gdc_reg ( |
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256 | const struct cirrus_board_str *fbst, |
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257 | unsigned int reg, |
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258 | unsigned int val) |
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259 | { |
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260 | fb_cirrus_write_reg8(fbst, GDC_INDEX, reg); |
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261 | fb_cirrus_write_reg8(fbst, GDC_DATA, val); |
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262 | } |
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263 | |
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264 | static inline unsigned int |
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265 | fb_cirrus_read_gdc_reg ( |
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266 | const struct cirrus_board_str *fbst, |
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267 | unsigned int reg) |
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268 | { |
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269 | fb_cirrus_write_reg8(fbst, GDC_INDEX, reg); |
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270 | return fb_cirrus_read_reg8(fbst, GDC_DATA); |
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271 | } |
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272 | |
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273 | #define VGA_DAC_MASK 0x06 |
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274 | |
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275 | static inline void |
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276 | fb_cirrus_write_hdr_reg ( |
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277 | const struct cirrus_board_str *fbst, |
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278 | unsigned int val) |
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279 | { |
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280 | volatile unsigned int dummy __attribute__((unused)); |
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281 | dummy = fb_cirrus_read_reg8(fbst, VGA_DAC_MASK); |
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282 | dummy = fb_cirrus_read_reg8(fbst, VGA_DAC_MASK); |
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283 | dummy = fb_cirrus_read_reg8(fbst, VGA_DAC_MASK); |
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284 | dummy = fb_cirrus_read_reg8(fbst, VGA_DAC_MASK); |
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285 | fb_cirrus_write_reg8(fbst, VGA_DAC_MASK, val); |
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286 | } |
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287 | |
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288 | /* Functionality to support multiple VGA frame buffers can be added easily, |
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289 | * but is not supported at this moment because there is no need for two or |
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290 | * more "classic" VGA adapters. Multiple frame buffer drivers may be |
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291 | * implemented and If we had implement it they would be named as "/dev/fb0", |
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292 | * "/dev/fb1", "/dev/fb2" and so on. |
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293 | */ |
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294 | |
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295 | /* |
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296 | * fb_cirrus device driver INITIALIZE entry point. |
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297 | */ |
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298 | rtems_device_driver |
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299 | frame_buffer_initialize( |
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300 | rtems_device_major_number major, |
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301 | rtems_device_minor_number minor, |
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302 | void *arg |
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303 | ) |
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304 | { |
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305 | rtems_status_code status; |
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306 | int res; |
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307 | |
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308 | printk( "FB_CIRRUS -- driver initializing..\n" ); |
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309 | |
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310 | res = pci_find_device( |
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311 | CIRRUS_VENDOR_ID, |
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312 | CIRRUS_GD5446_DEVICE_ID, |
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313 | minor, |
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314 | &cirrus_board_info.pci_bus, |
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315 | &cirrus_board_info.pci_device, |
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316 | &cirrus_board_info.pci_function |
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317 | ); |
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318 | |
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319 | if ( res != PCIB_ERR_SUCCESS ) { |
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320 | printk( "FB_CIRRUS initialize -- device not found\n" ); |
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321 | |
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322 | return RTEMS_UNSATISFIED; |
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323 | } |
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324 | else{ |
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325 | printk( "FB_CIRRUS -- driver initializing..\n" ); |
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326 | /* |
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327 | * Register the device |
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328 | */ |
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329 | status = rtems_io_register_name (FRAMEBUFFER_DEVICE_0_NAME, major, 0); |
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330 | if (status != RTEMS_SUCCESSFUL) { |
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331 | printk("Error registering " FRAMEBUFFER_DEVICE_0_NAME |
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332 | " FB_CIRRUS framebuffer device!\n"); |
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333 | rtems_fatal_error_occurred( status ); |
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334 | } |
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335 | |
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336 | _Atomic_Flag_clear(&driver_mutex, ATOMIC_ORDER_RELEASE); |
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337 | |
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338 | return RTEMS_SUCCESSFUL; |
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339 | } |
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340 | } |
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341 | |
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342 | /* |
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343 | * This function is used to initialize the Start Address - the first |
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344 | * displayed location in the video memory. |
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345 | * Usually mandatory |
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346 | */ |
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347 | static void |
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348 | cirrus_adjust_frame( struct cirrus_board_str *board, int x, int y) |
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349 | { |
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350 | uint32_t Base; |
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351 | uint8_t tmp; |
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352 | |
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353 | Base = ((y * fb_var.xres + x) >> 3); |
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354 | if (fb_var.bits_per_pixel != 1) |
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355 | Base *= (fb_var.bits_per_pixel >> 2); |
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356 | |
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357 | printk("FB_CIRRUS: cirrus_adjust_frame %d %d >>> %d %x\n", x, y, Base, Base); |
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358 | |
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359 | if ((Base & ~0x000FFFFF) != 0) { |
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360 | printk("FB_CIRRUS: Internal error: cirrus_adjust_frame: cannot handle overflow\n"); |
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361 | return; |
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362 | } |
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363 | |
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364 | fb_cirrus_write_crt_reg( board, 0x0C, (Base >> 8) & 0xff); |
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365 | fb_cirrus_write_crt_reg( board, 0x0D, Base & 0xff); |
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366 | |
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367 | tmp = fb_cirrus_read_crt_reg( board, 0x1B); |
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368 | tmp &= 0xF2; |
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369 | tmp |= (Base >> 16) & 0x01; |
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370 | tmp |= (Base >> 15) & 0x0C; |
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371 | fb_cirrus_write_crt_reg( board, 0x1B, tmp); |
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372 | |
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373 | tmp = fb_cirrus_read_crt_reg( board, 0x1D); |
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374 | tmp &= 0x7F; |
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375 | tmp |= (Base >> 12) & 0x80; |
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376 | fb_cirrus_write_crt_reg( board, 0x1D, tmp); |
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377 | } |
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378 | |
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379 | static int |
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380 | cirrus_set_mode(DisplayModePtr mode) |
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381 | { |
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382 | int depthcode = fb_var.bits_per_pixel;; |
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383 | int width; |
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384 | int HDiv2 = 0, VDiv2 = 0; |
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385 | const struct cirrus_board_str *cirrus_board_ptr = &cirrus_board_info; |
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386 | int temp; |
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387 | int hdr = -1; |
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388 | |
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389 | printk("FB_CIRRUS: mode %d bpp, %d Hz %d %d %d %d %d %d %d %d\n", |
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390 | fb_var.bits_per_pixel, |
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391 | mode->Clock, |
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392 | mode->HDisplay, |
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393 | mode->HSyncStart, |
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394 | mode->HSyncEnd, |
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395 | mode->HTotal, |
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396 | mode->VDisplay, |
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397 | mode->VSyncStart, |
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398 | mode->VSyncEnd, |
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399 | mode->VTotal); |
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400 | |
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401 | if ( mode->Clock > 85500 ) { |
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402 | /* The actual DAC register value is set later. */ |
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403 | /* The CRTC is clocked at VCLK / 2, so we must half the */ |
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404 | /* horizontal timings. */ |
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405 | if (!mode->CrtcHAdjusted) { |
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406 | mode->HDisplay >>= 1; |
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407 | mode->HSyncStart >>= 1; |
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408 | mode->HTotal >>= 1; |
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409 | mode->HSyncEnd >>= 1; |
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410 | mode->SynthClock >>= 1; |
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411 | mode->CrtcHAdjusted = TRUE; |
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412 | } |
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413 | depthcode += 64; |
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414 | HDiv2 = 1; |
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415 | } |
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416 | if (mode->VTotal >= 1024 ) { |
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417 | /* For non-interlaced vertical timing >= 1024, the vertical timings */ |
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418 | /* are divided by 2 and VGA CRTC 0x17 bit 2 is set. */ |
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419 | if (!mode->CrtcVAdjusted) { |
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420 | mode->VDisplay >>= 1; |
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421 | mode->VSyncStart >>= 1; |
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422 | mode->VSyncEnd >>= 1; |
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423 | mode->VTotal >>= 1; |
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424 | mode->CrtcVAdjusted = TRUE; |
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425 | } |
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426 | VDiv2 = 1; |
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427 | } |
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428 | |
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429 | /**************************************************** |
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430 | * Sequential registers |
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431 | */ |
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432 | fb_cirrus_write_seq_reg(cirrus_board_ptr, 0x00, 0x00); |
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433 | fb_cirrus_write_seq_reg(cirrus_board_ptr, 0x01, 0x01); |
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434 | fb_cirrus_write_seq_reg(cirrus_board_ptr, 0x02, 0x0F); |
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435 | fb_cirrus_write_seq_reg(cirrus_board_ptr, 0x03, 0x00); |
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436 | fb_cirrus_write_seq_reg(cirrus_board_ptr, 0x04, 0x0E); |
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437 | |
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438 | /**************************************************** |
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439 | * CRTC Controller Registers |
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440 | */ |
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441 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x00, (mode->HTotal >> 3) - 5 ); |
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442 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x01, (mode->HDisplay >> 3) - 1); |
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443 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x02, (mode->HSyncStart >> 3) - 1); |
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444 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x03, ((mode->HSyncEnd >> 3) & 0x1F) | 0x80); |
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445 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x04, (mode->HSyncStart >> 3)); |
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446 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x05, |
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447 | (((mode->HSyncEnd >> 3) & 0x20 ) << 2 ) |
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448 | | (((mode->HSyncEnd >> 3)) & 0x1F)); |
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449 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x06, (mode->VTotal - 2) & 0xFF); |
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450 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x07, |
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451 | (((mode->VTotal -2) & 0x100) >> 8 ) |
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452 | | (((mode->VDisplay -1) & 0x100) >> 7 ) |
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453 | | ((mode->VSyncStart & 0x100) >> 6 ) |
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454 | | (((mode->VSyncStart) & 0x100) >> 5 ) |
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455 | | 0x10 |
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456 | | (((mode->VTotal -2) & 0x200) >> 4 ) |
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457 | | (((mode->VDisplay -1) & 0x200) >> 3 ) |
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458 | | ((mode->VSyncStart & 0x200) >> 2 )); |
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459 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x08, 0x00); |
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460 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x09, ((mode->VSyncStart & 0x200) >>4) | 0x40); |
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461 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x0A, 0x00); |
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462 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x0B, 0x00); |
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463 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x0C, 0x00); |
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464 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x0D, 0x00); |
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465 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x0E, 0x00); |
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466 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x0F, 0x00); |
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467 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x10, mode->VSyncStart & 0xFF); |
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468 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x11, (mode->VSyncEnd & 0x0F) | 0x20); |
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469 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x12, (mode->VDisplay -1) & 0xFF); |
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470 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x13, 0x00); /* no interlace */ |
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471 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x14, 0x00); |
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472 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x15, mode->VSyncStart & 0xFF); |
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473 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x16, (mode->VSyncStart +1) & 0xFF); |
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474 | |
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475 | temp = 0xAF; |
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476 | if(VDiv2) |
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477 | temp |= 0x04; |
---|
478 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x17, temp); |
---|
479 | |
---|
480 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x18, 0xFF); |
---|
481 | |
---|
482 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x1A , |
---|
483 | (((mode->HTotal >> 3) & 0xC0 ) >> 2) |
---|
484 | | (((mode->VTotal - 2) & 0x300 ) >> 2)); |
---|
485 | |
---|
486 | width = fb_fix.line_length >> 3; |
---|
487 | if (fb_var.bits_per_pixel == 1) |
---|
488 | width <<= 2; |
---|
489 | if(width >= 0xFF) |
---|
490 | printk("FB_CIRRUS: Warning line size over the limit ... reduce bpp or width resolution"); |
---|
491 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x13, width); |
---|
492 | /* Offset extension (see CR13) */ |
---|
493 | temp = fb_cirrus_read_crt_reg( cirrus_board_ptr, 0x1B); |
---|
494 | temp &= 0xAF; |
---|
495 | temp |= (width >> (3+4)) & 0x10; |
---|
496 | temp |= (width >> (3+3)) & 0x40; |
---|
497 | temp |= 0x22; |
---|
498 | fb_cirrus_write_crt_reg( cirrus_board_ptr, 0x1B, temp); |
---|
499 | |
---|
500 | /**************************************************** |
---|
501 | * Sequential register |
---|
502 | * Enable linear mode and high-res packed pixel mode |
---|
503 | */ |
---|
504 | temp = fb_cirrus_read_seq_reg( cirrus_board_ptr, 0x07); |
---|
505 | temp &= 0xe0; |
---|
506 | switch (depthcode) { |
---|
507 | case 1: |
---|
508 | case 4: |
---|
509 | temp |= 0x10; |
---|
510 | break; |
---|
511 | case 8: |
---|
512 | temp |= 0x11; |
---|
513 | break; |
---|
514 | case 64+8: |
---|
515 | temp |= 0x17; |
---|
516 | break; |
---|
517 | case 15: |
---|
518 | temp |= 0x17; |
---|
519 | hdr = 0xC0; /* 5:5:5 Sierra */ |
---|
520 | break; |
---|
521 | case 16: |
---|
522 | temp |= 0x17; |
---|
523 | hdr = 0xC1; /* 5:6:5 XGA mode */ |
---|
524 | break; |
---|
525 | case 24: |
---|
526 | temp |= 0x15; |
---|
527 | hdr = 0xC5; /* 8:8:8 16M colors */ |
---|
528 | break; |
---|
529 | case 32: |
---|
530 | temp |= 0x19; |
---|
531 | hdr = 0xC5; /* 8:8:8 16M colors */ |
---|
532 | break; |
---|
533 | default: |
---|
534 | printk("FB_CIRRUS: Cannot Initialize display to requested mode\n"); |
---|
535 | printk("FB_CIRRUS: returning RTEMS_UNSATISFIED on depthcode %d\n", depthcode); |
---|
536 | return RTEMS_UNSATISFIED; |
---|
537 | } |
---|
538 | fb_cirrus_write_seq_reg( cirrus_board_ptr, 0x07, temp); |
---|
539 | /* this just set packed pixel mode with according bpp */ |
---|
540 | |
---|
541 | /**************************************************** |
---|
542 | * HDR Register |
---|
543 | */ |
---|
544 | if(hdr > 0) |
---|
545 | fb_cirrus_write_hdr_reg( cirrus_board_ptr, hdr); |
---|
546 | |
---|
547 | /**************************************************** |
---|
548 | * Graphic Data Controller Registers |
---|
549 | */ |
---|
550 | temp = fb_cirrus_read_gdc_reg( cirrus_board_ptr, 0x12); |
---|
551 | if (HDiv2) |
---|
552 | temp |= 0x20; |
---|
553 | else |
---|
554 | temp &= ~0x20; |
---|
555 | fb_cirrus_write_gdc_reg( cirrus_board_ptr, 0x12, temp); |
---|
556 | |
---|
557 | /* Enable high-color modes */ |
---|
558 | fb_cirrus_write_gdc_reg(cirrus_board_ptr, 0x05, 0x40); |
---|
559 | |
---|
560 | /* VGA graphics mode */ |
---|
561 | fb_cirrus_write_gdc_reg(cirrus_board_ptr, 0x06, 0x01); |
---|
562 | |
---|
563 | return TRUE; |
---|
564 | } |
---|
565 | |
---|
566 | static void |
---|
567 | cirrus_prepare_mode( void ) |
---|
568 | { |
---|
569 | |
---|
570 | active_mode = &available_modes[CIRRUS_DISPLAY_MODE]; |
---|
571 | |
---|
572 | fb_var.bits_per_pixel = CIRRUS_DEFAULT_BPP; |
---|
573 | |
---|
574 | fb_var.xres = active_mode->HDisplay; |
---|
575 | fb_var.yres = active_mode->VDisplay; |
---|
576 | |
---|
577 | fb_fix.line_length = (fb_var.xres * fb_var.bits_per_pixel + 7) / 8; |
---|
578 | |
---|
579 | fb_fix.type = FB_TYPE_PACKED_PIXELS; |
---|
580 | fb_fix.visual = FB_VISUAL_TRUECOLOR; |
---|
581 | |
---|
582 | } |
---|
583 | |
---|
584 | /* |
---|
585 | * fb_cirrus device driver OPEN entry point |
---|
586 | */ |
---|
587 | rtems_device_driver |
---|
588 | frame_buffer_open( |
---|
589 | rtems_device_major_number major, |
---|
590 | rtems_device_minor_number minor, |
---|
591 | void *arg |
---|
592 | ) |
---|
593 | { |
---|
594 | int r; |
---|
595 | uint32_t smem_start, regs_start; |
---|
596 | |
---|
597 | if (_Atomic_Flag_test_and_set(&driver_mutex, ATOMIC_ORDER_ACQUIRE) != 0 ) { |
---|
598 | printk( "FB_CIRRUS could not lock driver_mutex\n" ); |
---|
599 | |
---|
600 | return RTEMS_UNSATISFIED; |
---|
601 | } |
---|
602 | |
---|
603 | r = cirrus_pci_read(&cirrus_board_info, &smem_start, ®s_start); |
---|
604 | if ( r == RTEMS_UNSATISFIED ) |
---|
605 | return RTEMS_UNSATISFIED; |
---|
606 | |
---|
607 | fb_fix.smem_start = (volatile char *)smem_start; |
---|
608 | fb_fix.smem_len = 0x1000000; |
---|
609 | cirrus_board_info.reg_base = (void *)regs_start; |
---|
610 | |
---|
611 | cirrus_prepare_mode(); |
---|
612 | |
---|
613 | cirrus_set_mode( active_mode ); |
---|
614 | |
---|
615 | cirrus_adjust_frame( &cirrus_board_info, 0, 0); |
---|
616 | |
---|
617 | if (1) { |
---|
618 | uint32_t pixmask; |
---|
619 | int x, y; |
---|
620 | |
---|
621 | if(fb_var.bits_per_pixel == 32) |
---|
622 | pixmask = 0xffffff; |
---|
623 | else |
---|
624 | pixmask = (1 << fb_var.bits_per_pixel) - 1; |
---|
625 | |
---|
626 | printk("FB_CIRRUS: mode set, test patter output\n"); |
---|
627 | |
---|
628 | for(y = 0; y < fb_var.yres; y++) { |
---|
629 | for(x = 0; x < fb_var.xres; x++) { |
---|
630 | uint32_t color; |
---|
631 | char *addr = (char *)fb_fix.smem_start; |
---|
632 | addr += y * fb_fix.line_length; |
---|
633 | addr += x * fb_var.bits_per_pixel / 8; |
---|
634 | color = x & 1 ? 0 : y & 1 ? pixmask & 0x000ff00f : pixmask; |
---|
635 | if(y == fb_var.yres - 1) { |
---|
636 | if((x > 0) && (x < fb_var.xres-1)) |
---|
637 | color = pixmask & 0x00555555; |
---|
638 | } |
---|
639 | switch (fb_var.bits_per_pixel) { |
---|
640 | case 8: *(volatile uint8_t*) addr = color; |
---|
641 | break; |
---|
642 | case 16: *(volatile uint16_t*) addr = color; |
---|
643 | break; |
---|
644 | case 24: *(volatile uint32_t*) addr = |
---|
645 | (*(volatile uint32_t*) addr & 0xff000000) | color; |
---|
646 | break; |
---|
647 | case 32: *(volatile uint32_t*) addr = color; |
---|
648 | break; |
---|
649 | } |
---|
650 | } |
---|
651 | } |
---|
652 | } |
---|
653 | |
---|
654 | return RTEMS_SUCCESSFUL; |
---|
655 | |
---|
656 | } |
---|
657 | |
---|
658 | /* |
---|
659 | * fb_cirrus device driver CLOSE entry point |
---|
660 | */ |
---|
661 | rtems_device_driver |
---|
662 | frame_buffer_close( |
---|
663 | rtems_device_major_number major, |
---|
664 | rtems_device_minor_number minor, |
---|
665 | void *arg |
---|
666 | ) |
---|
667 | { |
---|
668 | _Atomic_Flag_clear(&driver_mutex, ATOMIC_ORDER_RELEASE); |
---|
669 | |
---|
670 | /* restore previous state. for VGA this means return to text mode. |
---|
671 | * leave out if graphics hardware has been initialized in |
---|
672 | * frame_buffer_initialize() */ |
---|
673 | |
---|
674 | /* VGA text mode */ |
---|
675 | fb_cirrus_write_gdc_reg(&cirrus_board_info, 0x06, 0x00); |
---|
676 | |
---|
677 | printk( "FB_CIRRUS: close called.\n" ); |
---|
678 | return RTEMS_SUCCESSFUL; |
---|
679 | } |
---|
680 | |
---|
681 | /* |
---|
682 | * fb_cirrus device driver READ entry point. |
---|
683 | */ |
---|
684 | rtems_device_driver |
---|
685 | frame_buffer_read( |
---|
686 | rtems_device_major_number major, |
---|
687 | rtems_device_minor_number minor, |
---|
688 | void *arg |
---|
689 | ) |
---|
690 | { |
---|
691 | rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *)arg; |
---|
692 | rw_args->bytes_moved = ((rw_args->offset + rw_args->count) > fb_fix.smem_len ) ? (fb_fix.smem_len - rw_args->offset) : rw_args->count; |
---|
693 | memcpy(rw_args->buffer, (const void *) (fb_fix.smem_start + rw_args->offset), rw_args->bytes_moved); |
---|
694 | return RTEMS_SUCCESSFUL; |
---|
695 | } |
---|
696 | |
---|
697 | /* |
---|
698 | * frame_buffer device driver WRITE entry point. |
---|
699 | */ |
---|
700 | rtems_device_driver |
---|
701 | frame_buffer_write( |
---|
702 | rtems_device_major_number major, |
---|
703 | rtems_device_minor_number minor, |
---|
704 | void *arg |
---|
705 | ) |
---|
706 | { |
---|
707 | rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *)arg; |
---|
708 | rw_args->bytes_moved = ((rw_args->offset + rw_args->count) > fb_fix.smem_len ) ? (fb_fix.smem_len - rw_args->offset) : rw_args->count; |
---|
709 | memcpy( (void *) (fb_fix.smem_start + rw_args->offset), rw_args->buffer, rw_args->bytes_moved); |
---|
710 | return RTEMS_SUCCESSFUL; |
---|
711 | } |
---|
712 | |
---|
713 | static int |
---|
714 | get_fix_screen_info( struct fb_fix_screeninfo *info ) |
---|
715 | { |
---|
716 | *info = fb_fix; |
---|
717 | return 0; |
---|
718 | } |
---|
719 | |
---|
720 | static int |
---|
721 | get_var_screen_info( struct fb_var_screeninfo *info ) |
---|
722 | { |
---|
723 | *info = fb_var; |
---|
724 | return 0; |
---|
725 | } |
---|
726 | |
---|
727 | /* |
---|
728 | * IOCTL entry point -- This method is called to carry |
---|
729 | * all services of this interface. |
---|
730 | */ |
---|
731 | rtems_device_driver |
---|
732 | frame_buffer_control( |
---|
733 | rtems_device_major_number major, |
---|
734 | rtems_device_minor_number minor, |
---|
735 | void *arg |
---|
736 | ) |
---|
737 | { |
---|
738 | rtems_libio_ioctl_args_t *args = arg; |
---|
739 | |
---|
740 | printk( "FB_CIRRUS ioctl called, cmd=%x\n", args->command ); |
---|
741 | |
---|
742 | switch( args->command ) { |
---|
743 | case FBIOGET_FSCREENINFO: |
---|
744 | args->ioctl_return = get_fix_screen_info( ( struct fb_fix_screeninfo * ) args->buffer ); |
---|
745 | break; |
---|
746 | case FBIOGET_VSCREENINFO: |
---|
747 | args->ioctl_return = get_var_screen_info( ( struct fb_var_screeninfo * ) args->buffer ); |
---|
748 | break; |
---|
749 | case FBIOPUT_VSCREENINFO: |
---|
750 | /* not implemented yet */ |
---|
751 | args->ioctl_return = -1; |
---|
752 | return RTEMS_UNSATISFIED; |
---|
753 | case FBIOGETCMAP: |
---|
754 | /* no palette - truecolor mode */ |
---|
755 | args->ioctl_return = -1; |
---|
756 | return RTEMS_UNSATISFIED; |
---|
757 | case FBIOPUTCMAP: |
---|
758 | /* no palette - truecolor mode */ |
---|
759 | args->ioctl_return = -1; |
---|
760 | return RTEMS_UNSATISFIED; |
---|
761 | default: |
---|
762 | args->ioctl_return = 0; |
---|
763 | break; |
---|
764 | } |
---|
765 | return RTEMS_SUCCESSFUL; |
---|
766 | } |
---|