1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup pc386_3c509 |
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5 | * |
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6 | * @brief 3C509 PC card support. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. |
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11 | * |
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12 | * Redistribution and use in source and binary forms, with or without |
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13 | * modification, are permitted provided that the following conditions are |
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14 | * met: 1. Redistributions of source code must retain the above copyright |
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15 | * notice, this list of conditions and the following disclaimer. 2. The name |
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16 | * of the author may not be used to endorse or promote products derived from |
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17 | * this software without specific prior written permission |
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18 | * |
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19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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20 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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21 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO |
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22 | * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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23 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
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24 | * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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25 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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26 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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27 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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29 | * |
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30 | * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by: |
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31 | * |
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32 | October 2, 1994 |
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33 | |
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34 | Modified by: Andres Vega Garcia |
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35 | |
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36 | INRIA - Sophia Antipolis, France |
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37 | e-mail: avega@sophia.inria.fr |
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38 | finger: avega@pax.inria.fr |
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39 | |
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40 | */ |
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41 | /* |
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42 | * Promiscuous mode added and interrupt logic slightly changed |
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43 | * to reduce the number of adapter failures. Transceiver select |
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44 | * logic changed to use value from EEPROM. Autoconfiguration |
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45 | * features added. |
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46 | * Done by: |
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47 | * Serge Babkin |
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48 | * Chelindbank (Chelyabinsk, Russia) |
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49 | * babkin@hq.icb.chel.su |
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50 | */ |
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51 | |
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52 | /* |
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53 | * Pccard support for 3C589 by: |
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54 | * HAMADA Naoki |
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55 | * nao@tom-yam.or.jp |
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56 | */ |
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57 | |
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58 | /** |
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59 | * @defgroup pc386_3c509 3C509 Support |
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60 | * |
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61 | * @ingroup i386_pc386 |
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62 | * |
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63 | * @brief 3C509 support. |
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64 | */ |
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65 | |
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66 | /* |
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67 | typedef unsigned short u_short; |
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68 | typedef unsigned long u_long; |
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69 | typedef unsigned char u_char; |
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70 | */ |
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71 | |
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72 | /* |
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73 | * Some global constants |
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74 | */ |
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75 | #define F_RX_FIRST 0x1 |
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76 | #define F_PROMISC 0x8 |
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77 | #define F_ACCESS_32_BITS 0x100 |
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78 | |
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79 | #define TX_INIT_RATE 16 |
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80 | #define TX_INIT_MAX_RATE 64 |
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81 | #define RX_INIT_LATENCY 64 |
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82 | #define RX_INIT_EARLY_THRESH 208 /* not less than MINCLSIZE */ |
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83 | #define RX_NEXT_EARLY_THRESH 500 |
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84 | |
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85 | #define EEPROMSIZE 0x40 |
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86 | #define MAX_EEPROMBUSY 1000 |
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87 | #define EP_LAST_TAG 0xd7 |
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88 | #define EP_MAX_BOARDS 16 |
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89 | /* |
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90 | * This `ID' port is a mere hack. There's currently no chance to register |
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91 | * it with config's idea of the ports that are in use. |
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92 | * |
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93 | * "After the automatic configuration is completed, the IDS is in its initial |
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94 | * state (ID-WAIT), and it monitors all write access to I/O port 01x0h, where |
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95 | * 'x' is any hex digit. If a zero is written to any one of these ports, then |
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96 | * that address is remembered and becomes the ID port. A second zero written |
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97 | * to that port resets the ID sequence to its initial state. The IDS watches |
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98 | * for the ID sequence to be written to the ID port." |
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99 | * |
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100 | * We prefer 0x110 over 0x100 so to not conflict with the Plaque&Pray |
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101 | * ports. |
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102 | */ |
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103 | #define EP_ID_PORT 0x110 |
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104 | #define EP_IOSIZE 16 /* 16 bytes of I/O space used. */ |
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105 | |
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106 | /* |
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107 | * some macros to acces long named fields |
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108 | */ |
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109 | #define IS_BASE (is->id_iobase) |
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110 | #define BASE (sc->ep_io_addr) |
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111 | |
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112 | /* |
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113 | * Commands to read/write EEPROM trough EEPROM command register (Window 0, |
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114 | * Offset 0xa) |
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115 | */ |
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116 | #define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ |
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117 | #define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ |
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118 | #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ |
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119 | #define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ |
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120 | |
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121 | #define EEPROM_BUSY (1<<15) |
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122 | #define EEPROM_TST_MODE (1<<14) |
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123 | |
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124 | /* |
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125 | * Some short functions, worth to let them be a macro |
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126 | */ |
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127 | #define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) |
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128 | #define GO_WINDOW(x) outw(BASE+EP_COMMAND, WINDOW_SELECT|(x)) |
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129 | |
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130 | /************************************************************************** |
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131 | * * |
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132 | * These define the EEPROM data structure. They are used in the probe |
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133 | * function to verify the existence of the adapter after having sent |
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134 | * the ID_Sequence. |
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135 | * |
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136 | * There are others but only the ones we use are defined here. |
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137 | * |
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138 | **************************************************************************/ |
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139 | |
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140 | #define EEPROM_NODE_ADDR_0 0x0 /* Word */ |
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141 | #define EEPROM_NODE_ADDR_1 0x1 /* Word */ |
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142 | #define EEPROM_NODE_ADDR_2 0x2 /* Word */ |
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143 | #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ |
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144 | #define EEPROM_MFG_ID 0x7 /* 0x6d50 */ |
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145 | #define EEPROM_ADDR_CFG 0x8 /* Base addr */ |
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146 | #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ |
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147 | |
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148 | /************************************************************************** |
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149 | * * |
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150 | * These are the registers for the 3Com 3c509 and their bit patterns when * |
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151 | * applicable. They have been taken out the the "EtherLink III Parallel * |
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152 | * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * |
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153 | * from 3com. * |
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154 | * * |
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155 | **************************************************************************/ |
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156 | |
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157 | #define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a |
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158 | * command reg. */ |
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159 | #define EP_STATUS 0x0e /* Read. BASE+0x0e is always status |
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160 | * reg. */ |
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161 | #define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window |
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162 | * reg. */ |
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163 | /* |
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164 | * Window 0 registers. Setup. |
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165 | */ |
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166 | /* Write */ |
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167 | #define EP_W0_EEPROM_DATA 0x0c |
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168 | #define EP_W0_EEPROM_COMMAND 0x0a |
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169 | #define EP_W0_RESOURCE_CFG 0x08 |
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170 | #define EP_W0_ADDRESS_CFG 0x06 |
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171 | #define EP_W0_CONFIG_CTRL 0x04 |
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172 | /* Read */ |
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173 | #define EP_W0_PRODUCT_ID 0x02 |
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174 | #define EP_W0_MFG_ID 0x00 |
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175 | |
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176 | /* |
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177 | * Window 1 registers. Operating Set. |
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178 | */ |
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179 | /* Write */ |
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180 | #define EP_W1_TX_PIO_WR_2 0x02 |
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181 | #define EP_W1_TX_PIO_WR_1 0x00 |
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182 | /* Read */ |
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183 | #define EP_W1_FREE_TX 0x0c |
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184 | #define EP_W1_TX_STATUS 0x0b /* byte */ |
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185 | #define EP_W1_TIMER 0x0a /* byte */ |
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186 | #define EP_W1_RX_STATUS 0x08 |
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187 | #define EP_W1_RX_PIO_RD_2 0x02 |
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188 | #define EP_W1_RX_PIO_RD_1 0x00 |
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189 | |
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190 | /* |
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191 | * Window 2 registers. Station Address Setup/Read |
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192 | */ |
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193 | /* Read/Write */ |
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194 | #define EP_W2_ADDR_5 0x05 |
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195 | #define EP_W2_ADDR_4 0x04 |
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196 | #define EP_W2_ADDR_3 0x03 |
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197 | #define EP_W2_ADDR_2 0x02 |
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198 | #define EP_W2_ADDR_1 0x01 |
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199 | #define EP_W2_ADDR_0 0x00 |
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200 | |
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201 | /* |
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202 | * Window 3 registers. FIFO Management. |
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203 | */ |
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204 | /* Read */ |
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205 | #define EP_W3_FREE_TX 0x0c |
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206 | #define EP_W3_FREE_RX 0x0a |
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207 | |
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208 | /* |
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209 | * Window 4 registers. Diagnostics. |
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210 | */ |
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211 | /* Read/Write */ |
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212 | #define EP_W4_MEDIA_TYPE 0x0a |
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213 | #define EP_W4_CTRLR_STATUS 0x08 |
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214 | #define EP_W4_NET_DIAG 0x06 |
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215 | #define EP_W4_FIFO_DIAG 0x04 |
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216 | #define EP_W4_HOST_DIAG 0x02 |
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217 | #define EP_W4_TX_DIAG 0x00 |
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218 | |
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219 | /* |
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220 | * Window 5 Registers. Results and Internal status. |
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221 | */ |
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222 | /* Read */ |
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223 | #define EP_W5_READ_0_MASK 0x0c |
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224 | #define EP_W5_INTR_MASK 0x0a |
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225 | #define EP_W5_RX_FILTER 0x08 |
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226 | #define EP_W5_RX_EARLY_THRESH 0x06 |
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227 | #define EP_W5_TX_AVAIL_THRESH 0x02 |
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228 | #define EP_W5_TX_START_THRESH 0x00 |
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229 | |
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230 | /* |
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231 | * Window 6 registers. Statistics. |
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232 | */ |
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233 | /* Read/Write */ |
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234 | #define TX_TOTAL_OK 0x0c |
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235 | #define RX_TOTAL_OK 0x0a |
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236 | #define TX_DEFERRALS 0x08 |
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237 | #define RX_FRAMES_OK 0x07 |
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238 | #define TX_FRAMES_OK 0x06 |
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239 | #define RX_OVERRUNS 0x05 |
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240 | #define TX_COLLISIONS 0x04 |
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241 | #define TX_AFTER_1_COLLISION 0x03 |
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242 | #define TX_AFTER_X_COLLISIONS 0x02 |
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243 | #define TX_NO_SQE 0x01 |
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244 | #define TX_CD_LOST 0x00 |
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245 | |
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246 | /**************************************** |
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247 | * |
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248 | * Register definitions. |
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249 | * |
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250 | ****************************************/ |
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251 | |
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252 | /* |
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253 | * Command register. All windows. |
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254 | * |
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255 | * 16 bit register. |
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256 | * 15-11: 5-bit code for command to be executed. |
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257 | * 10-0: 11-bit arg if any. For commands with no args; |
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258 | * this can be set to anything. |
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259 | */ |
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260 | #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms |
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261 | * after issuing */ |
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262 | #define WINDOW_SELECT (u_short) (0x1<<11) |
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263 | #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to |
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264 | * determine whether |
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265 | * this is needed. If |
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266 | * so; wait 800 uSec |
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267 | * before using trans- |
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268 | * ceiver. */ |
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269 | #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on |
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270 | * power-up */ |
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271 | #define RX_ENABLE (u_short) (0x4<<11) |
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272 | #define RX_RESET (u_short) (0x5<<11) |
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273 | #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) |
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274 | #define TX_ENABLE (u_short) (0x9<<11) |
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275 | #define TX_DISABLE (u_short) (0xa<<11) |
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276 | #define TX_RESET (u_short) (0xb<<11) |
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277 | #define REQ_INTR (u_short) (0xc<<11) |
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278 | #define SET_INTR_MASK (u_short) (0xe<<11) |
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279 | #define SET_RD_0_MASK (u_short) (0xf<<11) |
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280 | #define SET_RX_FILTER (u_short) (0x10<<11) |
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281 | #define FIL_INDIVIDUAL (u_short) (0x1) |
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282 | #define FIL_GROUP (u_short) (0x2) |
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283 | #define FIL_BRDCST (u_short) (0x4) |
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284 | #define FIL_ALL (u_short) (0x8) |
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285 | #define SET_RX_EARLY_THRESH (u_short) (0x11<<11) |
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286 | #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) |
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287 | #define SET_TX_START_THRESH (u_short) (0x13<<11) |
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288 | #define STATS_ENABLE (u_short) (0x15<<11) |
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289 | #define STATS_DISABLE (u_short) (0x16<<11) |
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290 | #define STOP_TRANSCEIVER (u_short) (0x17<<11) |
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291 | /* |
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292 | * The following C_* acknowledge the various interrupts. Some of them don't |
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293 | * do anything. See the manual. |
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294 | */ |
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295 | #define ACK_INTR (u_short) (0x6800) |
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296 | #define C_INTR_LATCH (u_short) (ACK_INTR|0x1) |
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297 | #define C_CARD_FAILURE (u_short) (ACK_INTR|0x2) |
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298 | #define C_TX_COMPLETE (u_short) (ACK_INTR|0x4) |
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299 | #define C_TX_AVAIL (u_short) (ACK_INTR|0x8) |
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300 | #define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) |
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301 | #define C_RX_EARLY (u_short) (ACK_INTR|0x20) |
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302 | #define C_INT_RQD (u_short) (ACK_INTR|0x40) |
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303 | #define C_UPD_STATS (u_short) (ACK_INTR|0x80) |
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304 | #define C_MASK (u_short) 0xFF /* mask of C_* */ |
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305 | |
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306 | /* |
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307 | * Status register. All windows. |
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308 | * |
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309 | * 15-13: Window number(0-7). |
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310 | * 12: Command_in_progress. |
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311 | * 11: reserved. |
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312 | * 10: reserved. |
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313 | * 9: reserved. |
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314 | * 8: reserved. |
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315 | * 7: Update Statistics. |
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316 | * 6: Interrupt Requested. |
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317 | * 5: RX Early. |
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318 | * 4: RX Complete. |
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319 | * 3: TX Available. |
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320 | * 2: TX Complete. |
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321 | * 1: Adapter Failure. |
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322 | * 0: Interrupt Latch. |
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323 | */ |
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324 | #define S_INTR_LATCH (u_short) (0x1) |
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325 | #define S_CARD_FAILURE (u_short) (0x2) |
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326 | #define S_TX_COMPLETE (u_short) (0x4) |
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327 | #define S_TX_AVAIL (u_short) (0x8) |
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328 | #define S_RX_COMPLETE (u_short) (0x10) |
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329 | #define S_RX_EARLY (u_short) (0x20) |
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330 | #define S_INT_RQD (u_short) (0x40) |
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331 | #define S_UPD_STATS (u_short) (0x80) |
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332 | #define S_MASK (u_short) 0xFF /* mask of S_* */ |
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333 | #define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\ |
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334 | S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY) |
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335 | #define S_COMMAND_IN_PROGRESS (u_short) (0x1000) |
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336 | |
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337 | /* Address Config. Register. |
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338 | * Window 0/Port 06 |
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339 | */ |
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340 | |
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341 | #define ACF_CONNECTOR_BITS 14 |
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342 | #define ACF_CONNECTOR_UTP 0 |
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343 | #define ACF_CONNECTOR_AUI 1 |
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344 | #define ACF_CONNECTOR_BNC 3 |
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345 | |
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346 | /* Resource configuration register. |
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347 | * Window 0/Port 08 |
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348 | * |
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349 | */ |
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350 | |
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351 | #define SET_IRQ(base,irq) outw((base) + EP_W0_RESOURCE_CFG, \ |
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352 | ((inw((base) + EP_W0_RESOURCE_CFG) & 0x0fff) | \ |
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353 | ((u_short)(irq)<<12)) ) /* set IRQ i */ |
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354 | |
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355 | /* |
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356 | * FIFO Registers. |
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357 | * RX Status. Window 1/Port 08 |
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358 | * |
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359 | * 15: Incomplete or FIFO empty. |
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360 | * 14: 1: Error in RX Packet 0: Incomplete or no error. |
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361 | * 13-11: Type of error. |
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362 | * 1000 = Overrun. |
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363 | * 1011 = Run Packet Error. |
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364 | * 1100 = Alignment Error. |
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365 | * 1101 = CRC Error. |
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366 | * 1001 = Oversize Packet Error (>1514 bytes) |
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367 | * 0010 = Dribble Bits. |
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368 | * (all other error codes, no errors.) |
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369 | * |
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370 | * 10-0: RX Bytes (0-1514) |
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371 | */ |
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372 | #define ERR_RX_INCOMPLETE (u_short) (0x1<<15) |
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373 | #define ERR_RX (u_short) (0x1<<14) |
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374 | #define ERR_RX_OVERRUN (u_short) (0x8<<11) |
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375 | #define ERR_RX_RUN_PKT (u_short) (0xb<<11) |
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376 | #define ERR_RX_ALIGN (u_short) (0xc<<11) |
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377 | #define ERR_RX_CRC (u_short) (0xd<<11) |
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378 | #define ERR_RX_OVERSIZE (u_short) (0x9<<11) |
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379 | #define ERR_RX_DRIBBLE (u_short) (0x2<<11) |
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380 | |
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381 | /* |
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382 | * FIFO Registers. |
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383 | * TX Status. Window 1/Port 0B |
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384 | * |
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385 | * Reports the transmit status of a completed transmission. Writing this |
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386 | * register pops the transmit completion stack. |
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387 | * |
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388 | * Window 1/Port 0x0b. |
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389 | * |
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390 | * 7: Complete |
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391 | * 6: Interrupt on successful transmission requested. |
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392 | * 5: Jabber Error (TP Only, TX Reset required. ) |
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393 | * 4: Underrun (TX Reset required. ) |
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394 | * 3: Maximum Collisions. |
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395 | * 2: TX Status Overflow. |
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396 | * 1-0: Undefined. |
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397 | * |
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398 | */ |
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399 | #define TXS_COMPLETE 0x80 |
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400 | #define TXS_SUCCES_INTR_REQ 0x40 |
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401 | #define TXS_JABBER 0x20 |
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402 | #define TXS_UNDERRUN 0x10 |
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403 | #define TXS_MAX_COLLISION 0x8 |
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404 | #define TXS_STATUS_OVERFLOW 0x4 |
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405 | |
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406 | /* |
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407 | * Configuration control register. |
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408 | * Window 0/Port 04 |
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409 | */ |
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410 | /* Read */ |
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411 | #define IS_AUI (1<<13) |
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412 | #define IS_BNC (1<<12) |
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413 | #define IS_UTP (1<<9) |
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414 | /* Write */ |
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415 | #define ENABLE_DRQ_IRQ 0x0001 |
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416 | #define W0_P4_CMD_RESET_ADAPTER 0x4 |
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417 | #define W0_P4_CMD_ENABLE_ADAPTER 0x1 |
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418 | /* |
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419 | * Media type and status. |
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420 | * Window 4/Port 0A |
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421 | */ |
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422 | #define ENABLE_UTP 0xc0 |
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423 | #define DISABLE_UTP 0x0 |
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424 | |
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425 | /* |
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426 | * Misc defines for various things. |
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427 | */ |
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428 | #define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */ |
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429 | #define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */ |
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430 | #define PROD_ID 0x9150 |
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431 | |
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432 | #define AUI 0x1 |
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433 | #define BNC 0x2 |
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434 | #define UTP 0x4 |
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435 | |
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436 | #define RX_BYTES_MASK (u_short) (0x07ff) |
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