source: rtems/c/src/lib/libbsp/i386/i386ex/start/start.s @ 2c3840b

4.104.114.84.95
Last change on this file since 2c3840b was 2c3840b, checked in by Joel Sherrill <joel.sherrill@…>, on 09/30/98 at 20:58:39

Added new autoconf test for i386 code16/code32 support. The guts of the
test were suggested by Ian Taylor <ian@…> and Joel did the
hard part of putting it in aclocal and editting all the offending
Makefiles and source code which could use this feature.
  • Property mode set to 100644
File size: 12.4 KB
Line 
1/*
2 *  This file is the main boot and configuration file for the i386ex.  It is
3 *  solely responsible for initializing the internal register set to reflect
4 *  the proper board configuration.  This version is the "generic" i386ex
5 *  startup:   
6 *
7 *    1) 512K flask ROM @3f80000
8 *    2) 1 Mb RAM @ 0x0
9 *    3) Timer0 used as RTEMS clock ticker, 1 msec tick rate.
10 *    4) READY# is generated by CPU
11 *
12 *  The file is a multi-section file, with sections as follows:
13 *     1) interrupt gates,             in section "ints"
14 *     2) interrupt descriptor table,  in section "idt"
15 *     3) global descriptor table,     in section "gdt"
16 *     4) reset                        in section "reset"
17 *     5) and initial boot code        in section " initial"
18 *
19 *  Submitted by:
20 *
21 *    Erik Ivanenko
22 *    University of Toronto
23 *    erik.ivanenko@utoronto.ca
24 *
25 *  The license and distribution terms for this file may be
26 *  found in the file LICENSE in this distribution or at
27 *  http://www.OARcorp.com/rtems/license.html.
28 *
29 *  $Id$
30
31       
32changes:       
33    SetExRegByte(ICW3S  , 0x02 ) # MUST be 0x02 according to intel
34    SetExRegByte(ICW3M  , 0x04 ) # IR2 is cascaded internally: was 0x02 => IR1 is cascaded
35       
36 */
37
38#include "asm.h"
39#include "macros.inc"
40#include "80386ex.inc"
41
42/*
43 * NEXT_GAS Needed for binutils 2.9.1.0.7 and higher
44 */                     
45
46        EXTERN (boot_card)         /* exits to bspstart   */
47        EXTERN (stack_start)       /* defined in startup/linkcmds */
48        EXTERN (Clock_exit)
49
50        PUBLIC (Interrupt_descriptor_table)
51        PUBLIC ( SYM(IDTR) )
52        PUBLIC( SYM(_initInternalRegisters) )
53       
54BEGIN_DATA
55SYM(IDTR):      DESC3( SYM(Interrupt_descriptor_table), 0x07ff );
56       
57SYM(Interrupt_descriptor_table):   /* Now in data section */
58        .rept 256
59        .word 0,0,0,0
60        .endr
61
62END_DATA       
63       
64BEGIN_DATA
65         PUBLIC (_Global_descriptor_table)
66                       
67SYM(GDTR):      DESC3( GDT_TABLE, 0x1f ); # one less than the size
68SYM (_Global_descriptor_table):
69SYM(GDT_TABLE): DESC2(0,0,0,0,0,0);
70SYM(GDT_ALIAS): DESC2(32,0x1000,0x0,0x93,0,0x0);
71SYM(GDT_CODE):  DESC2(0xffff,0,0x0,0x9B,0xDF,0x00);
72SYM(GDT_DATA):  DESC2(0xffff,0,0x0,0x92,0xDF,0x00); # was CF
73SYM(GDT_END):
74
75END_DATA
76       
77
78/* This section is the section that is used by the interrupt
79   descriptor table.  It is used to provide the IDT with the
80   correct vector offsets.  It is for symbol definition only.
81*/
82       
83
84        .section .reset                       
85
86                PUBLIC ( SYM(reset) )
87SYM(reset):     
88        nop
89        cli
90        jmp     SYM(_initInternalRegisters) /* different section in this file */
91        .code32                             /* in case this section moves     */
92        nop                                 /* required by CHIP LAB to pad out size */
93        nop
94        nop
95        nop
96        nop
97
98       
99       
100        .section .initial
101       
102/*
103 * Enable access to peripheral register at expanded I/O addresses
104 */
105SYM(_initInternalRegisters):   
106        .code16
107        movw    $0x8000 , ax           
108        outb    al      , $REMAPCFGH
109        xchg    al      , ah
110        outb    al,$REMAPCFGL
111        outw    ax,      $REMAPCFG ;
112       
113
114/*
115 * Configure operation of the A20 Address Line
116 */     
117SYM(A20):
118        movw    $PORT92 , dx
119       
120        inb     dx      , al   # clear A20 port reset
121        andb    $0xfe   , al   # b0 Fast Reset(0)=disabled,(1)=reset triggered
122        orb     $0x02   , al   # Bit 1 Fast A20 = 0 (always 0) else enabled.
123        outb    al      , dx
124
125SYM(Watchdog):
126        movw    $WDTSTATUS      , dx    # address the WDT status port
127        inb     dx              , al    # get the WDT status
128        orb     $0x01           , al    # set the CLKDIS bit
129        outb    al              , dx    # disable the clock to the WDT
130
131/*
132 * Initialize Refresh Control Unit for:
133 *      Refresh Address = 0x0000
134
135 *      Refresh gate between rows is 15.6 uSec
136 *      Using a CLK2 frequency of 50Mhz ( 25Mhz CPU )
137 *      The refresh unit is enabled
138 *      The refresh pin is not used.
139 */
140
141SYM(InitRCU):           
142        SetExRegWord( RFSCIR , 390)     # refresh interval was 390, tried 312
143        SetExRegWord( RFSBAD , 0x0)     # base address
144        SetExRegWord( RFSADD , 0x0)     # address register
145        SetExRegWord( RFSCON , 0x8000)  # enable bit
146
147/*
148 * Initialize clock and power mgmt unit for:   
149 *      Clock Frequency = 50 Mhz
150 *      Prescaled clock output = 1 Mhz
151 *      Normal halt instructions
152 */
153       
154SYM(InitClk):   
155        SetExRegByte( PWRCON, 0x0 )
156        SetExRegWord( CLKPRS, 0x17)   # 0x13 for 1.19318 MHz.  0x17 for 1MHz.
157
158/**************************************************************
159 * Initialize the Pin Configurations
160 *************************************************************/
161
162/*
163 *      Initialize I/O port 1 for:     
164 *      PIN 0 = 1,      DCD0# to package pin
165 *      PIN 1 = 1,      RTS0# to package pin
166 *      PIN 2 = 1,      DTR0# to package pin
167 *      PIN 3 = 1,      DSR0# to package pin
168 *      PIN 4 = 1,      RI0# to package pin
169 *      PIN 5 = 0,      Outport (FLASH Vpp Enable, 0=Enable 1=Disable)
170 *      PIN 6 = 0,      Outport (P16_HOLD to 386ex option header JP7 pin 5)
171 *      PIN 7 = 0,      Outport (P17_HOLD to 386ex option header JP7 pin 3)
172 */
173
174SYM(InitPort1):         
175        SetExRegByte( P1LTC     , 0xff )
176        SetExRegByte( P1DIR     , 0x0  )
177        SetExRegByte( P1CFG     , 0x1f)
178       
179/*
180 *      Initialize I/O port 2 for:     
181 *      PIN 0 = 0,      Outport (P20_CS0# to 386ex option header JP7 pin 11)
182 *      PIN 1 = 0,      Outport (P21_CS1# to 386ex option header JP7 pin 9)
183 *      PIN 2 = 1,      CS2# (SMRAM) If not using CS2 can be configured as.?
184 *      PIN 3 = 0,      Outport ( no connect )
185 *      PIN 4 = 1,      CS#4 (DRAM)
186 *      PIN 5 = 1,      RXD0 input. See not for I/0 port 1 pins 1-4
187 *      PIN 6 = 1,      TXD0 output.
188 *      PIN 7 = 1,      CTS0# input.
189 */
190       
191SYM(InitPort2):
192        SetExRegByte( P2LTC     , 0xff )
193        SetExRegByte( P2DIR     , 0x0  )
194        SetExRegByte( P2CFG     , 0xfe)
195       
196/*
197 *      Initialize I/O port 3 P3CFG     
198 *      PIN 0 = 1,      TMROUT0 to package pin
199 *      PIN 1 = 0,      (TMROUT1 to 386ex option header JP7 pin 23)
200 *      PIN 2 = 0,      INT0 (IR1) disabled, (P3.2 out to JP7 pin 21)
201 *      PIN 3 = 0,      INT1 (IR5) disbled (P3.3  to option header JP7 pin 19)
202 *      PIN 4 = 0,      INT2 (IR6) disbled (P3.4 to option header JP7 pin 17)
203 *      PIN 5 = 0,      INT2 (IR7) disabled (P3.5 to 386ex header JP7 pin 15)
204 *      PIN 6 = 0,      Inport (Debugger Break P3.6/PWRD to package pin )
205 *                      P3.6 selected
206 *      PIN 7 = 0,      COMCLK output disabled, 1.8432 Mhz OSC1 oscillator.
207 *                      ( Debbugger uses COMCLK as the clocking source )
208 *                      P3.7 connected to package pin.
209 */
210       
211SYM(InitPort3):         
212        SetExRegByte( P3LTC     , 0xff )
213        SetExRegByte( P3DIR     , 0x41 )
214        SetExRegByte( P3CFG     , 0x09 )  # can check TMROUT0
215/*
216 *      Initialize Peripheral Pin Configurations:       
217 *      PIN 0 = 1,      RTS1# to package pin   
218 *      PIN 1 = 1,      DTR1# to package pin
219 *      PIN 2 = 1,      TXD1 out to package pin
220 *      PIN 3 = 0,      EOP#/TC
221 *      PIN 4 = 0,      DACK0#
222 *      PIN 5 = 1,      Timer2
223 *      PIN 6 = 0,      0 => CS6# connected to package pin
224 *      PIN 7 = 0,      Don't care
225 */
226       
227SYM(InitPeriph):       
228        SetExRegByte( PINCFG , 0x24)
229       
230/*
231 *      Initialize the Asynchronous Serial Ports:       
232 *      BIT 7 = 1,      Internal SIO1 modem signals
233 *      BIT 6 = 1,      Internal SIO0 modem signals
234 *      BIT 2 = 0,      PSCLK for SSIO clock
235 *      BIT 1 = 1,      SERCLK for SIO1 clock
236 *      BIT 0 = 1,      SERCLK for SIO0 clock
237 */
238
239SYM(InitSIO):   
240        SetExRegByte( SIOCFG, 0xC3 ) # SIOn clocked internally
241
242        SetExRegByte( LCR0,     0x80 )  # latch DLL0, DLH0
243        SetExRegByte( DLL0, 0x51 )      # 0x51 sets to 9600 baud 0x7 -> 115,200
244        SetExRegByte( DLH0, 0x00 )  # 0x145 is 2400 baud
245        SetExRegByte( LCR0, 0x03 )  # enable r/w buffers, IER0 accessible
246                                    # mode 8-n-1
247        SetExRegByte( IER0, 0x00 )  # was 0x0f All interrupts detected
248       
249        SetExRegByte( LCR1, 0x80 )  # latch DLL0, DLH0
250        SetExRegByte( DLL1, 0x51 )  # 0x51 set to 9600 baud, 0x7 = 115200
251        SetExRegByte( DLH1, 0x00 )  # 0x145 is 2400 baud
252        SetExRegByte( LCR1, 0x03 )  # enable r/w buffers, IER1 accessible
253                                        # reg 8-n-1
254        SetExRegByte( IER1, 0x00 )  # was 0x0f - All interrupts detected
255
256SYM(InitMCR):   
257/*
258 *      Initialize Timer for:   
259 *      BIT 7 = 1,      Timer clocks disabled
260 *      BIT 6 = 0,      Reserved
261 *      BIT 5 = 1,      TMRCLK2 instead of Vcc to Gate2
262 *      BIT 4 = 0,      PSCLK to CLK2
263 *      BIT 3 = 1,      TMRCLK1 instead of Vcc to Gate1
264 *      BIT 2 = 0,      PSCLK to Gate1
265 *      BIT 1 = 0,      Vcc to Gate0   
266 *      BIT 0 = 0,      PSCLK to Gate0
267 */
268
269SYM(InitTimer):
270        SetExRegByte(TMRCFG , 0x80 ) # All counters disabled, Gates 0,1
271                                     # and 2 are set to Vcc
272
273        SetExRegByte(TMRCON , 0x34 ) # prepare to write counter 0 LSB,MSB
274        SetExRegByte(TMR0   , 0x00 ) # sfa
275        SetExRegByte(TMR0   , 0x00 ) # sfa
276
277                       
278        SetExRegByte(TMRCON , 0x70 ) # mode 0 disables on Gate= Vcc
279        SetExRegByte(TMR1   , 0x00 ) # sfa
280        SetExRegByte(TMR1   , 0x00 ) # sfa
281       
282        SetExRegByte(TMRCON , 0xB0 ) # mode 0 disables on gate =Vcc
283        SetExRegByte(TMR2   , 0x00 ) # 
284        SetExRegByte(TMR2   , 0x00 ) # 
285
286        SetExRegByte(TMRCFG , 0x80 ) # Enable = 0x00
287
288/*
289 *      Initialize the DMACFG register for:     
290 *      BIT 7    = 1  , Disable DACK#1
291 *      BITs 6:4 = 100, TMROUT2 connected to DRQ1
292 *      BIT 3    = 1  , Disable DACK0#
293 *      BIT 2:0  = 000, Pin is connected to DRQ0
294 */
295
296        SetExRegByte(DMACFG , 0xC0  )
297        SetExRegByte(DMACMD1, 0x00 ) # disable both DMA channels
298        SetExRegByte(DMAMOD1, 0x40 )
299/*
300 *      Initialize the INTCFG register for:
301 *      BIT 7 = 0,      8259 cascade disabled
302 *      BIT 3 = 0,      SLAVE IR6 connected to Vss
303 *      BIT 2 = 0,      SLAVE IR5 connected to Vss
304 *      BIT 1 = 0,      SLAVE IR1 connected to SSIOINT
305 *      BIT 0 = 0,      SLAVE IR0 connected to Vss
306 */
307
308SYM(InitInt):
309       
310        cli                               # !
311       
312        SetExRegByte(ICW1S  , 0x11 ) # EDGE TRIGGERED
313        SetExRegByte(ICW2S  , 0x28 ) # Slave base vector after Master
314        SetExRegByte(ICW3S  , 0x02 ) # slave cascaded to IR2 on master
315        SetExRegByte(ICW4S  , 0x01 ) # must be 0x01
316
317        SetExRegByte(ICW1M  , 0x11 ) # edge triggered
318        SetExRegByte(ICW2M  , 0x20 ) # base vector starts at byte 32
319        SetExRegByte(ICW3M  , 0x04)  # IR2 is cascaded internally
320        SetExRegByte(ICW4M  , 0x01 ) # idem
321       
322        SetExRegByte(OCW1M  , 0xde ) # IR0  only = 0xfe.  for IR5 and IR0 active use 0xde
323        SetExRegByte(INTCFG , 0x00 )
324       
325        movw    $0xFFFB, SYM(i8259s_cache) /* set up same values in cache */
326       
327SYM(SetCS4):   
328        SetExRegWord(CS4ADL , 0x702)         #Configure chip select 4
329        SetExRegWord(CS4ADH , 0x00)
330        SetExRegWord(CS4MSKH, 0x03F)     
331        SetExRegWord(CS4MSKL, 0xFC01) 
332
333SYM(SetUCS1):           
334        SetExRegWord(UCSADL , 0x0304)      # 512K block starting at 0x80000 until 0x3f80000
335        SetExRegWord(UCSADH , 0x03F8)
336        SetExRegWord(UCSMSKH, 0x03F7)   
337        SetExRegWord(UCSMSKL, 0xFC01)     # configure upper chip select
338
339/******************************************************
340* The GDT must be in RAM since it must be writeable,
341* So, move the whole data section down.
342********************************************************/
343
344        movw $ _ram_data_offset , di
345        movw $ _ram_data_segment, cx
346        mov  cx                 , es
347
348        movw $ _data_size       , cx
349        movw $ _rom_data_segment, ax
350        movw $ _rom_data_offset , si
351        mov  ax                 , ds
352       
353        repne
354        movsb
355       
356/*****************************
357 * Load the Global Descriptor
358 * Table Register
359 ****************************/
360       
361#ifdef NEXT_GAS
362        data32
363        addr32
364#endif 
365        lgdt SYM(GDTR) #  location of GDT
366
367       
368SYM(SetUCS):           
369        SetExRegWord(UCSADL, 0x0702)      # now 512K starting at 0x3f80000.     
370        SetExRegWord(UCSADH, 0x03f8)
371        SetExRegWord(UCSMSKH, 0x0007)   
372        SetExRegWord(UCSMSKL, 0xFC01)     # configure upper chip select
373
374/***************************
375 * Switch to Protected Mode
376 ***************************/
377        mov     cr0, eax
378        orw     $0x1, ax
379        mov     eax, cr0
380       
381/**************************
382 * Flush prefetch queue,
383 * and load CS selector
384 *********************/
385
386        ljmpl $ GDT_CODE_PTR , $  SYM(_load_segment_registers) # sets the code selector
387       
388/*
389 * Load the segment registers
390 */
391SYM(_load_segment_registers):   
392        .code32
393        pLOAD_SEGMENT( GDT_DATA_PTR, fs)
394        pLOAD_SEGMENT( GDT_DATA_PTR, gs)
395        pLOAD_SEGMENT( GDT_DATA_PTR, ss)
396        pLOAD_SEGMENT( GDT_DATA_PTR, ds)
397        pLOAD_SEGMENT( GDT_DATA_PTR, es)
398       
399/*
400 *  Set up the stack
401 */
402
403SYM(lidtr):
404        lidt    SYM(IDTR)
405
406SYM (_establish_stack):
407        movl    $end, eax               # stack starts right after bss
408        movl    $stack_origin, esp      # this is the high starting address
409        movl    $stack_origin, ebp
410/*
411 *  Zero out the BSS segment
412 */
413SYM (zero_bss):
414        cld                             # make direction flag count up
415        movl    $ SYM (end),ecx        # find end of .bss
416        movl    $ SYM (_bss_start),edi # edi = beginning of .bss
417        subl    edi,ecx               # ecx = size of .bss in bytes
418        shrl    ecx                    # size of .bss in longs
419        shrl    ecx
420        xorl    eax,eax               # value to clear out memory
421        repne                           # while ecx != 0
422        stosl                           #   clear a long in the bss
423
424/*
425 *  Transfer control to User's Board Support Package
426 */
427        pushl   $0                       # environp
428        pushl   $0                       # argv
429        pushl   $0                       # argc
430        call SYM(boot_card)
431        addl    $12,esp
432
433        cli                              # stops interrupts from being processed after hlt!
434        hlt                              # shutdown
435
436END
437
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