| 1 | /* |
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| 2 | * This file is the main boot and configuration file for the i386ex. It is |
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| 3 | * solely responsible for initializing the internal register set to reflect |
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| 4 | * the proper board configuration. This version is the "generic" i386ex |
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| 5 | * startup: |
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| 6 | * |
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| 7 | * 1) 512K flask ROM @3f80000 |
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| 8 | * 2) 1 Mb RAM @ 0x0 |
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| 9 | * 3) Timer0 used as RTEMS clock ticker, 1 msec tick rate. |
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| 10 | * 4) READY# is generated by CPU |
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| 11 | * |
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| 12 | * The file is a multi-section file, with sections as follows: |
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| 13 | * 1) interrupt gates, in section "ints" |
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| 14 | * 2) interrupt descriptor table, in section "idt" |
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| 15 | * 3) global descriptor table, in section "gdt" |
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| 16 | * 4) reset in section "reset" |
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| 17 | * 5) and initial boot code in section " initial" |
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| 18 | * |
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| 19 | * Submitted by: |
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| 20 | * |
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| 21 | * Erik Ivanenko |
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| 22 | * University of Toronto |
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| 23 | * erik.ivanenko@utoronto.ca |
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| 24 | * |
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| 25 | * The license and distribution terms for this file may be |
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| 26 | * found in the file LICENSE in this distribution or at |
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| 27 | * http://www.rtems.com/license/LICENSE. |
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| 28 | * |
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| 29 | * $Id$ |
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| 30 | |
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| 31 | |
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| 32 | changes: |
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| 33 | SetExRegByte(ICW3S , 0x02 ) # MUST be 0x02 according to intel |
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| 34 | SetExRegByte(ICW3M , 0x04 ) # IR2 is cascaded internally: was 0x02 => IR1 is cascaded |
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| 35 | |
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| 36 | */ |
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| 37 | |
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| 38 | |
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| 39 | #include "asm.h" |
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| 40 | #include "macros.inc" |
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| 41 | #include "80386ex.inc" |
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| 42 | |
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| 43 | |
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| 44 | /* |
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| 45 | * NEW_GAS Needed for binutils 2.9.1.0.7 and higher |
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| 46 | */ |
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| 47 | |
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| 48 | EXTERN (boot_card) /* exits to bspstart */ |
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| 49 | EXTERN (stack_start) /* defined in startup/linkcmds */ |
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| 50 | EXTERN (Clock_exit) |
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| 51 | |
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| 52 | PUBLIC (Interrupt_descriptor_table) |
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| 53 | PUBLIC ( SYM(IDTR) ) |
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| 54 | /* PUBLIC( SYM(_initInternalRegisters) ) */ |
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| 55 | |
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| 56 | BEGIN_DATA |
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| 57 | SYM(IDTR): DESC3( SYM(Interrupt_descriptor_table), 0x07ff ); |
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| 58 | |
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| 59 | SYM(Interrupt_descriptor_table): /* Now in data section */ |
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| 60 | .rept 256 |
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| 61 | .word 0,0,0,0 |
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| 62 | .endr |
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| 63 | |
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| 64 | END_DATA |
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| 65 | |
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| 66 | BEGIN_DATA |
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| 67 | PUBLIC (_Global_descriptor_table) |
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| 68 | |
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| 69 | SYM(GDTR): DESC3( GDT_TABLE, 0x1f ); # one less than the size |
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| 70 | SYM (_Global_descriptor_table): |
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| 71 | SYM(GDT_TABLE): DESC2(0,0,0,0,0,0); |
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| 72 | SYM(GDT_ALIAS): DESC2(32,0x1000,0x0,0x93,0,0x0); |
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| 73 | SYM(GDT_CODE): DESC2(0xffff,0,0x0,0x9B,0xDF,0x00); |
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| 74 | SYM(GDT_DATA): DESC2(0xffff,0,0x0,0x92,0xDF,0x00); # was CF |
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| 75 | SYM(GDT_END): |
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| 76 | |
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| 77 | END_DATA |
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| 78 | |
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| 79 | |
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| 80 | /* This section is the section that is used by the interrupt |
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| 81 | descriptor table. It is used to provide the IDT with the |
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| 82 | correct vector offsets. It is for symbol definition only. |
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| 83 | */ |
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| 84 | |
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| 85 | .code16 |
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| 86 | .section .reset, "ax" |
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| 87 | PUBLIC ( SYM(reset) ) |
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| 88 | SYM(reset): |
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| 89 | nop |
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| 90 | cli |
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| 91 | #ifdef NEW_GAS |
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| 92 | data32 addr32 jmp SYM(_initInternalRegisters) /* different section in this file */ |
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| 93 | #else |
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| 94 | jmp SYM(_initInternalRegisters) /* different section in this file */ |
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| 95 | #endif |
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| 96 | /* .code32 in case this section moves */ |
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| 97 | nop /* required by CHIP LAB to pad out size */ |
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| 98 | nop |
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| 99 | nop |
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| 100 | nop |
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| 101 | nop |
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| 102 | nop |
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| 103 | nop |
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| 104 | nop |
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| 105 | nop |
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| 106 | nop |
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| 107 | nop |
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| 108 | |
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| 109 | .section .initial, "ax" |
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| 110 | /* nop */ /* required for linker -- initial jump is to "label - 2" */ |
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| 111 | /* nop */ /* ie. _initInternalRegisters -2 ( which now == .initial ) */ |
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| 112 | /* |
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| 113 | * Enable access to peripheral register at expanded I/O addresses |
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| 114 | */ |
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| 115 | SYM(_initInternalRegisters): |
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| 116 | |
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| 117 | /* .code16 */ |
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| 118 | movw $0x8000 , ax |
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| 119 | outb al , $REMAPCFGH |
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| 120 | xchg al , ah |
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| 121 | outb al,$REMAPCFGL |
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| 122 | outw ax, $REMAPCFG ; |
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| 123 | /* |
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| 124 | * Configure operation of the A20 Address Line |
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| 125 | */ |
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| 126 | SYM(A20): |
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| 127 | movw $PORT92 , dx |
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| 128 | |
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| 129 | inb dx , al # clear A20 port reset |
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| 130 | andb $0xfe , al # b0 Fast Reset(0)=disabled,(1)=reset triggered |
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| 131 | orb $0x02 , al # Bit 1 Fast A20 = 0 (always 0) else enabled. |
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| 132 | outb al , dx |
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| 133 | |
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| 134 | |
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| 135 | SYM(Watchdog): |
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| 136 | movw $WDTSTATUS , dx # address the WDT status port |
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| 137 | inb dx , al # get the WDT status |
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| 138 | orb $0x01 , al # set the CLKDIS bit |
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| 139 | outb al , dx # disable the clock to the WDT |
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| 140 | |
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| 141 | /* |
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| 142 | * Initialize Refresh Control Unit for: |
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| 143 | * Refresh Address = 0x0000 |
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| 144 | |
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| 145 | * Refresh gate between rows is 15.6 uSec |
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| 146 | * Using a CLK2 frequency of 50Mhz ( 25Mhz CPU ) |
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| 147 | * The refresh unit is enabled |
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| 148 | * The refresh pin is not used. |
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| 149 | */ |
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| 150 | |
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| 151 | SYM(InitRCU): |
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| 152 | SetExRegWord( RFSCIR , 390) # refresh interval was 390, tried 312 |
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| 153 | SetExRegWord( RFSBAD , 0x0) # base address |
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| 154 | SetExRegWord( RFSADD , 0x0) # address register |
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| 155 | SetExRegWord( RFSCON , 0x8000) # enable bit |
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| 156 | |
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| 157 | /* |
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| 158 | * Initialize clock and power mgmt unit for: |
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| 159 | * Clock Frequency = 50 Mhz |
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| 160 | * Prescaled clock output = 1 Mhz |
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| 161 | * Normal halt instructions |
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| 162 | */ |
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| 163 | |
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| 164 | SYM(InitClk): |
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| 165 | SetExRegByte( PWRCON, 0x0 ) |
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| 166 | SetExRegWord( CLKPRS, 0x17) # 0x13 for 1.19318 MHz. 0x17 for 1MHz. |
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| 167 | |
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| 168 | /************************************************************** |
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| 169 | * Initialize the Pin Configurations |
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| 170 | *************************************************************/ |
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| 171 | |
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| 172 | /* |
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| 173 | * Initialize I/O port 1 for: |
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| 174 | * PIN 0 = 1, DCD0# to package pin |
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| 175 | * PIN 1 = 1, RTS0# to package pin |
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| 176 | * PIN 2 = 1, DTR0# to package pin |
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| 177 | * PIN 3 = 1, DSR0# to package pin |
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| 178 | * PIN 4 = 1, RI0# to package pin |
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| 179 | * PIN 5 = 0, Outport (FLASH Vpp Enable, 0=Enable 1=Disable) |
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| 180 | * PIN 6 = 0, Outport (P16_HOLD to 386ex option header JP7 pin 5) |
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| 181 | * PIN 7 = 0, Outport (P17_HOLD to 386ex option header JP7 pin 3) |
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| 182 | */ |
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| 183 | |
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| 184 | SYM(InitPort1): |
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| 185 | SetExRegByte( P1LTC , 0xff ) |
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| 186 | SetExRegByte( P1DIR , 0x0 ) |
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| 187 | SetExRegByte( P1CFG , 0x1f) |
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| 188 | |
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| 189 | /* |
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| 190 | * Initialize I/O port 2 for: |
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| 191 | * PIN 0 = 0, Outport (P20_CS0# to 386ex option header JP7 pin 11) |
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| 192 | * PIN 1 = 0, Outport (P21_CS1# to 386ex option header JP7 pin 9) |
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| 193 | * PIN 2 = 1, CS2# (SMRAM) If not using CS2 can be configured as.? |
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| 194 | * PIN 3 = 0, Outport ( no connect ) |
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| 195 | * PIN 4 = 1, CS#4 (DRAM) |
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| 196 | * PIN 5 = 1, RXD0 input. See not for I/0 port 1 pins 1-4 |
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| 197 | * PIN 6 = 1, TXD0 output. |
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| 198 | * PIN 7 = 1, CTS0# input. |
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| 199 | */ |
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| 200 | |
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| 201 | SYM(InitPort2): |
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| 202 | SetExRegByte( P2LTC , 0xff ) |
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| 203 | SetExRegByte( P2DIR , 0x0 ) |
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| 204 | SetExRegByte( P2CFG , 0xfe) |
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| 205 | |
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| 206 | /* |
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| 207 | * Initialize I/O port 3 P3CFG |
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| 208 | * PIN 0 = 1, TMROUT0 to package pin |
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| 209 | * PIN 1 = 0, (TMROUT1 to 386ex option header JP7 pin 23) |
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| 210 | * PIN 2 = 0, INT0 (IR1) disabled, (P3.2 out to JP7 pin 21) |
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| 211 | * PIN 3 = 0, INT1 (IR5) disbled (P3.3 to option header JP7 pin 19) |
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| 212 | * PIN 4 = 0, INT2 (IR6) disbled (P3.4 to option header JP7 pin 17) |
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| 213 | * PIN 5 = 0, INT2 (IR7) disabled (P3.5 to 386ex header JP7 pin 15) |
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| 214 | * PIN 6 = 0, Inport (Debugger Break P3.6/PWRD to package pin ) |
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| 215 | * P3.6 selected |
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| 216 | * PIN 7 = 0, COMCLK output disabled, 1.8432 Mhz OSC1 oscillator. |
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| 217 | * ( Debbugger uses COMCLK as the clocking source ) |
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| 218 | * P3.7 connected to package pin. |
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| 219 | */ |
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| 220 | |
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| 221 | SYM(InitPort3): |
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| 222 | SetExRegByte( P3LTC , 0xff ) |
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| 223 | SetExRegByte( P3DIR , 0x41 ) |
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| 224 | SetExRegByte( P3CFG , 0x09 ) # can check TMROUT0 |
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| 225 | /* |
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| 226 | * Initialize Peripheral Pin Configurations: |
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| 227 | * PIN 0 = 1, RTS1# to package pin |
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| 228 | * PIN 1 = 1, DTR1# to package pin |
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| 229 | * PIN 2 = 1, TXD1 out to package pin |
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| 230 | * PIN 3 = 0, EOP#/TC |
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| 231 | * PIN 4 = 0, DACK0# |
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| 232 | * PIN 5 = 1, Timer2 |
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| 233 | * PIN 6 = 0, 0 => CS6# connected to package pin |
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| 234 | * PIN 7 = 0, Don't care |
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| 235 | */ |
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| 236 | |
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| 237 | SYM(InitPeriph): |
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| 238 | SetExRegByte( PINCFG , 0x24) |
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| 239 | |
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| 240 | /* |
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| 241 | * Initialize the Asynchronous Serial Ports: |
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| 242 | * BIT 7 = 1, Internal SIO1 modem signals |
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| 243 | * BIT 6 = 1, Internal SIO0 modem signals |
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| 244 | * BIT 2 = 0, PSCLK for SSIO clock |
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| 245 | * BIT 1 = 1, SERCLK for SIO1 clock |
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| 246 | * BIT 0 = 1, SERCLK for SIO0 clock |
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| 247 | */ |
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| 248 | |
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| 249 | SYM(InitSIO): |
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| 250 | SetExRegByte( SIOCFG, 0xC3 ) # SIOn clocked internally |
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| 251 | |
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| 252 | SetExRegByte( LCR0, 0x80 ) # latch DLL0, DLH0 |
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| 253 | SetExRegByte( DLL0, 0x51 ) # 0x51 sets to 9600 baud, 0x28=19.2k, 0x7 -> 115.2k |
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| 254 | SetExRegByte( DLH0, 0x00 ) # 0x145 is 2400 baud |
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| 255 | SetExRegByte( LCR0, 0x03 ) # enable r/w buffers, IER0 accessible |
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| 256 | # mode 8-n-1 |
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| 257 | SetExRegByte( IER0, 0x00 ) # was 0x0f All interrupts detected |
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| 258 | |
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| 259 | SetExRegByte( LCR1, 0x80 ) # latch DLL0, DLH0 |
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| 260 | SetExRegByte( DLL1, 0x51 ) # 0x51 set to 9600 baud, 0x7 = 115200 |
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| 261 | SetExRegByte( DLH1, 0x00 ) # 0x145 is 2400 baud |
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| 262 | SetExRegByte( LCR1, 0x03 ) # enable r/w buffers, IER1 accessible |
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| 263 | # reg 8-n-1 |
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| 264 | SetExRegByte( IER1, 0x00 ) # was 0x0f - All interrupts detected |
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| 265 | |
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| 266 | SYM(InitMCR): |
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| 267 | /* |
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| 268 | * Initialize Timer for: |
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| 269 | * BIT 7 = 1, Timer clocks disabled |
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| 270 | * BIT 6 = 0, Reserved |
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| 271 | * BIT 5 = 1, TMRCLK2 instead of Vcc to Gate2 |
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| 272 | * BIT 4 = 0, PSCLK to CLK2 |
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| 273 | * BIT 3 = 1, TMRCLK1 instead of Vcc to Gate1 |
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| 274 | * BIT 2 = 0, PSCLK to Gate1 |
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| 275 | * BIT 1 = 0, Vcc to Gate0 |
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| 276 | * BIT 0 = 0, PSCLK to Gate0 |
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| 277 | */ |
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| 278 | |
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| 279 | SYM(InitTimer): |
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| 280 | SetExRegByte(TMRCFG , 0x80 ) # All counters disabled, Gates 0,1 |
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| 281 | # and 2 are set to Vcc |
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| 282 | |
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| 283 | SetExRegByte(TMRCON , 0x34 ) # prepare to write counter 0 LSB,MSB |
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| 284 | SetExRegByte(TMR0 , 0x00 ) # sfa |
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| 285 | SetExRegByte(TMR0 , 0x00 ) # sfa |
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| 286 | |
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| 287 | |
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| 288 | SetExRegByte(TMRCON , 0x70 ) # mode 0 disables on Gate= Vcc |
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| 289 | SetExRegByte(TMR1 , 0x00 ) # sfa |
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| 290 | SetExRegByte(TMR1 , 0x00 ) # sfa |
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| 291 | |
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| 292 | SetExRegByte(TMRCON , 0xB0 ) # mode 0 disables on gate =Vcc |
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| 293 | SetExRegByte(TMR2 , 0x00 ) # |
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| 294 | SetExRegByte(TMR2 , 0x00 ) # |
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| 295 | |
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| 296 | SetExRegByte(TMRCFG , 0x80 ) # Enable = 0x00 |
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| 297 | |
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| 298 | /* |
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| 299 | * Initialize the DMACFG register for: |
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| 300 | * BIT 7 = 1 , Disable DACK#1 |
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| 301 | * BITs 6:4 = 100, TMROUT2 connected to DRQ1 |
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| 302 | * BIT 3 = 1 , Disable DACK0# |
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| 303 | * BIT 2:0 = 000, Pin is connected to DRQ0 |
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| 304 | */ |
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| 305 | |
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| 306 | SetExRegByte(DMACFG , 0xC0 ) |
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| 307 | SetExRegByte(DMACMD1, 0x00 ) # disable both DMA channels |
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| 308 | SetExRegByte(DMAMOD1, 0x40 ) |
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| 309 | /* |
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| 310 | * Initialize the INTCFG register for: |
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| 311 | * BIT 7 = 0, 8259 cascade disabled |
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| 312 | * BIT 3 = 0, SLAVE IR6 connected to Vss |
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| 313 | * BIT 2 = 0, SLAVE IR5 connected to Vss |
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| 314 | * BIT 1 = 0, SLAVE IR1 connected to SSIOINT |
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| 315 | * BIT 0 = 0, SLAVE IR0 connected to Vss |
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| 316 | */ |
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| 317 | |
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| 318 | SYM(InitInt): |
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| 319 | |
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| 320 | cli # ! |
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| 321 | /* SetExRegByte(OCW3S, 0x20) # address the Slave status port |
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| 322 | movw $OCW3S , dx |
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| 323 | inb dx , al # Read the IRR. |
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| 324 | |
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| 325 | SetExRegByte(OCW3M, 0x20) # address the Master status port |
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| 326 | movw $OCW3M , dx |
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| 327 | inb dx , al # Read the IRR. |
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| 328 | */ |
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| 329 | |
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| 330 | SetExRegByte(ICW1S , 0x11 ) # EDGE TRIGGERED |
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| 331 | SetExRegByte(ICW2S , 0x28 ) # Slave base vector after Master |
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| 332 | SetExRegByte(ICW3S , 0x02 ) # slave cascaded to IR2 on master |
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| 333 | SetExRegByte(ICW4S , 0x01 ) # must be 0x01 |
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| 334 | |
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| 335 | SetExRegByte(ICW1M , 0x11 ) # edge triggered |
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| 336 | SetExRegByte(ICW2M , 0x20 ) # base vector starts at byte 32 |
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| 337 | SetExRegByte(ICW3M , 0x04) # IR2 is cascaded internally |
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| 338 | SetExRegByte(ICW4M , 0x01 ) # fully nested mode |
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| 339 | |
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| 340 | SetExRegByte(OCW1M , 0xde ) # IR0 only = 0xfe. |
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| 341 | # for IR5 and IR0 active use 0xde |
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| 342 | # for IR0 and IR2 use 0xfa |
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| 343 | SetExRegByte(INTCFG , 0x00 ) |
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| 344 | |
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| 345 | |
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| 346 | SYM(SetCS4): |
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| 347 | SetExRegWord(CS4ADL , 0x702) #Configure chip select 4 |
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| 348 | SetExRegWord(CS4ADH , 0x00) |
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| 349 | SetExRegWord(CS4MSKH, 0x03F) |
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| 350 | SetExRegWord(CS4MSKL, 0xFC01) |
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| 351 | |
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| 352 | SYM(SetUCS1): |
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| 353 | SetExRegWord(UCSADL , 0x0304) # 512K block starting at 0x80000 until 0x3f80000 |
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| 354 | SetExRegWord(UCSADH , 0x03F8) |
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| 355 | SetExRegWord(UCSMSKH, 0x03F7) |
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| 356 | SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select |
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| 357 | |
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| 358 | /****************************************************** |
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| 359 | * The GDT must be in RAM since it must be writeable, |
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| 360 | * So, move the whole data section down. |
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| 361 | ********************************************************/ |
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| 362 | |
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| 363 | movw $ _ram_data_offset , di |
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| 364 | movw $ _ram_data_segment, cx |
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| 365 | mov cx , es |
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| 366 | |
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| 367 | movw $ _data_size , cx |
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| 368 | movw $ _rom_data_segment, ax |
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| 369 | movw $ _rom_data_offset , si |
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| 370 | mov ax , ds |
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| 371 | |
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| 372 | repne |
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| 373 | movsb |
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| 374 | |
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| 375 | /***************************** |
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| 376 | * Load the Global Descriptor |
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| 377 | * Table Register |
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| 378 | ****************************/ |
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| 379 | |
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| 380 | #ifdef NEW_GAS |
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| 381 | data32 addr32 lgdt SYM(GDTR) # location of GDT |
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| 382 | #else |
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| 383 | lgdt SYM(GDTR) # location of GDT |
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| 384 | #endif |
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| 385 | |
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| 386 | |
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| 387 | SYM(SetUCS): |
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| 388 | SetExRegWord(UCSADL, 0x0702) # now 512K starting at 0x3f80000. |
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| 389 | SetExRegWord(UCSADH, 0x03f8) |
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| 390 | SetExRegWord(UCSMSKH, 0x0007) |
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| 391 | SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select |
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| 392 | |
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| 393 | /* |
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| 394 | * SRAM chip select: 16 bit bus size,starting 16Mb, size 512k, |
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| 395 | * 4 waits |
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| 396 | */ |
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| 397 | |
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| 398 | #ifdef UT_I386EX |
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| 399 | |
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| 400 | SYM(SetCS1): |
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| 401 | SetExRegWord(CS1ADL, 0x0000) |
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| 402 | SetExRegWord(CS1ADH, 0x000E) |
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| 403 | SetExRegWord(CS1MSKH, 0x0000) |
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| 404 | SetExRegWord(CS1MSKL, 0x0001) |
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| 405 | |
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| 406 | SYM(SetCS2): |
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| 407 | SetExRegWord(CS2ADL, 0x0704) |
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| 408 | SetExRegWord(CS2ADH, 0x0100) |
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| 409 | SetExRegWord(CS2MSKH, 0x0003) |
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| 410 | SetExRegWord(CS2MSKL, 0xfc01) |
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| 411 | |
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| 412 | /* |
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| 413 | * Real-time clock: 8 bit bus size, starting@16Mb+512K, size 32k |
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| 414 | * 4 waits |
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| 415 | */ |
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| 416 | SYM(SetCS3): |
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| 417 | SetExRegWord(CS3ADL, 0x0504) |
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| 418 | SetExRegWord(CS3ADH, 0x0108) |
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| 419 | SetExRegWord(CS3MSKH, 0x0000) |
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| 420 | SetExRegWord(CS3MSKL, 0x7c01) |
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| 421 | |
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| 422 | #endif |
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| 423 | /*************************** |
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| 424 | * Switch to Protected Mode |
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| 425 | ***************************/ |
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| 426 | |
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| 427 | mov cr0, eax |
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| 428 | orw $0x1, ax |
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| 429 | mov eax, cr0 |
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| 430 | |
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| 431 | /************************** |
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| 432 | * Flush prefetch queue, |
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| 433 | * and load CS selector |
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| 434 | *********************/ |
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| 435 | |
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| 436 | ljmpl $ GDT_CODE_PTR , $ SYM(_load_segment_registers) # sets the code selector |
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| 437 | |
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| 438 | /* |
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| 439 | * Load the segment registers |
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| 440 | */ |
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| 441 | SYM(_load_segment_registers): |
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| 442 | .code32 |
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| 443 | pLOAD_SEGMENT( GDT_DATA_PTR, fs) |
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| 444 | pLOAD_SEGMENT( GDT_DATA_PTR, gs) |
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| 445 | pLOAD_SEGMENT( GDT_DATA_PTR, ss) |
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| 446 | pLOAD_SEGMENT( GDT_DATA_PTR, ds) |
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| 447 | pLOAD_SEGMENT( GDT_DATA_PTR, es) |
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| 448 | |
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| 449 | /* |
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| 450 | * Set up the stack |
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| 451 | */ |
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| 452 | |
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| 453 | SYM(lidtr): |
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| 454 | lidt SYM(IDTR) |
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| 455 | |
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| 456 | SYM (_establish_stack): |
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| 457 | movl $end, eax # stack starts right after bss |
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| 458 | movl $stack_origin, esp # this is the high starting address |
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| 459 | movl $stack_origin, ebp |
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| 460 | |
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| 461 | /* |
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| 462 | * Zero out the BSS segment |
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| 463 | */ |
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| 464 | SYM (zero_bss): |
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| 465 | cld # make direction flag count up |
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| 466 | movl $ SYM (end),ecx # find end of .bss |
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| 467 | movl $ SYM (_bss_start),edi # edi = beginning of .bss |
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| 468 | subl edi,ecx # ecx = size of .bss in bytes |
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| 469 | shrl ecx # size of .bss in longs |
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| 470 | shrl ecx |
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| 471 | xorl eax,eax # value to clear out memory |
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| 472 | repne # while ecx != 0 |
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| 473 | stosl # clear a long in the bss |
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| 474 | |
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| 475 | |
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| 476 | /* |
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| 477 | * Transfer control to User's Board Support Package |
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| 478 | */ |
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| 479 | pushl $0 # environp |
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| 480 | pushl $0 # argv |
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| 481 | pushl $0 # argc |
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| 482 | |
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| 483 | movw $0xFFFB, SYM(i8259s_cache) # ICU mask values reflect |
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| 484 | # initial ICU state |
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| 485 | call SYM(boot_card) |
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| 486 | addl $12,esp |
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| 487 | |
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| 488 | cli # stops interrupts from being processed after hlt! |
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| 489 | hlt # shutdown |
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| 490 | |
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| 491 | END |
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| 492 | |
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