1 | /* |
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2 | * This file is the main boot and configuration file for the i386ex. It is |
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3 | * solely responsible for initializing the internal register set to reflect |
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4 | * the proper board configuration. This version is the "generic" i386ex |
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5 | * startup: |
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6 | * |
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7 | * 1) 512K flask ROM @3f80000 |
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8 | * 2) 1 Mb RAM @ 0x0 |
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9 | * 3) Timer0 used as RTEMS clock ticker, 1 msec tick rate. |
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10 | * 4) READY# is generated by CPU |
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11 | * |
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12 | * The file is a multi-section file, with sections as follows: |
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13 | * 1) interrupt gates, in section "ints" |
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14 | * 2) interrupt descriptor table, in section "idt" |
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15 | * 3) global descriptor table, in section "gdt" |
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16 | * 4) reset in section "reset" |
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17 | * 5) and initial boot code in section " initial" |
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18 | * |
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19 | * Submitted by: |
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20 | * |
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21 | * Erik Ivanenko |
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22 | * University of Toronto |
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23 | * erik.ivanenko@utoronto.ca |
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24 | * |
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25 | * The license and distribution terms for this file may be |
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26 | * found in the file LICENSE in this distribution or at |
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27 | * http://www.OARcorp.com/rtems/license.html. |
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28 | * |
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29 | * $Id$ |
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30 | |
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31 | |
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32 | changes: |
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33 | SetExRegByte(ICW3S , 0x02 ) # MUST be 0x02 according to intel |
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34 | SetExRegByte(ICW3M , 0x04 ) # IR2 is cascaded internally: was 0x02 => IR1 is cascaded |
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35 | |
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36 | */ |
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37 | |
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38 | #include "asm.h" |
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39 | #include "macros.inc" |
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40 | #include "80386ex.inc" |
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41 | |
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42 | /* |
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43 | * NEW_GAS Needed for binutils 2.9.1.0.7 and higher |
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44 | */ |
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45 | |
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46 | EXTERN (boot_card) /* exits to bspstart */ |
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47 | EXTERN (stack_start) /* defined in startup/linkcmds */ |
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48 | EXTERN (Clock_exit) |
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49 | |
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50 | PUBLIC (Interrupt_descriptor_table) |
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51 | PUBLIC ( SYM(IDTR) ) |
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52 | PUBLIC( SYM(_initInternalRegisters) ) |
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53 | |
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54 | BEGIN_DATA |
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55 | SYM(IDTR): DESC3( SYM(Interrupt_descriptor_table), 0x07ff ); |
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56 | |
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57 | SYM(Interrupt_descriptor_table): /* Now in data section */ |
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58 | .rept 256 |
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59 | .word 0,0,0,0 |
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60 | .endr |
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61 | |
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62 | END_DATA |
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63 | |
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64 | BEGIN_DATA |
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65 | PUBLIC (_Global_descriptor_table) |
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66 | |
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67 | SYM(GDTR): DESC3( GDT_TABLE, 0x1f ); # one less than the size |
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68 | SYM (_Global_descriptor_table): |
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69 | SYM(GDT_TABLE): DESC2(0,0,0,0,0,0); |
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70 | SYM(GDT_ALIAS): DESC2(32,0x1000,0x0,0x93,0,0x0); |
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71 | SYM(GDT_CODE): DESC2(0xffff,0,0x0,0x9B,0xDF,0x00); |
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72 | SYM(GDT_DATA): DESC2(0xffff,0,0x0,0x92,0xDF,0x00); # was CF |
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73 | SYM(GDT_END): |
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74 | |
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75 | END_DATA |
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76 | |
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77 | |
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78 | /* This section is the section that is used by the interrupt |
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79 | descriptor table. It is used to provide the IDT with the |
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80 | correct vector offsets. It is for symbol definition only. |
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81 | */ |
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82 | |
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83 | |
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84 | .section .reset |
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85 | |
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86 | PUBLIC ( SYM(reset) ) |
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87 | SYM(reset): |
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88 | nop |
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89 | cli |
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90 | jmp SYM(_initInternalRegisters) /* different section in this file */ |
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91 | .code32 /* in case this section moves */ |
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92 | nop /* required by CHIP LAB to pad out size */ |
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93 | nop |
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94 | nop |
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95 | nop |
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96 | nop |
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97 | |
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98 | |
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99 | |
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100 | .section .initial |
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101 | |
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102 | /* |
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103 | * Enable access to peripheral register at expanded I/O addresses |
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104 | */ |
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105 | SYM(_initInternalRegisters): |
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106 | .code16 |
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107 | movw $0x8000 , ax |
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108 | outb al , $REMAPCFGH |
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109 | xchg al , ah |
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110 | outb al,$REMAPCFGL |
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111 | outw ax, $REMAPCFG ; |
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112 | |
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113 | |
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114 | /* |
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115 | * Configure operation of the A20 Address Line |
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116 | */ |
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117 | SYM(A20): |
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118 | movw $PORT92 , dx |
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119 | |
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120 | inb dx , al # clear A20 port reset |
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121 | andb $0xfe , al # b0 Fast Reset(0)=disabled,(1)=reset triggered |
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122 | orb $0x02 , al # Bit 1 Fast A20 = 0 (always 0) else enabled. |
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123 | outb al , dx |
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124 | |
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125 | SYM(Watchdog): |
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126 | movw $WDTSTATUS , dx # address the WDT status port |
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127 | inb dx , al # get the WDT status |
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128 | orb $0x01 , al # set the CLKDIS bit |
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129 | outb al , dx # disable the clock to the WDT |
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130 | |
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131 | /* |
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132 | * Initialize Refresh Control Unit for: |
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133 | * Refresh Address = 0x0000 |
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134 | |
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135 | * Refresh gate between rows is 15.6 uSec |
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136 | * Using a CLK2 frequency of 50Mhz ( 25Mhz CPU ) |
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137 | * The refresh unit is enabled |
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138 | * The refresh pin is not used. |
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139 | */ |
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140 | |
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141 | SYM(InitRCU): |
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142 | SetExRegWord( RFSCIR , 390) # refresh interval was 390, tried 312 |
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143 | SetExRegWord( RFSBAD , 0x0) # base address |
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144 | SetExRegWord( RFSADD , 0x0) # address register |
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145 | SetExRegWord( RFSCON , 0x8000) # enable bit |
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146 | |
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147 | /* |
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148 | * Initialize clock and power mgmt unit for: |
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149 | * Clock Frequency = 50 Mhz |
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150 | * Prescaled clock output = 1 Mhz |
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151 | * Normal halt instructions |
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152 | */ |
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153 | |
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154 | SYM(InitClk): |
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155 | SetExRegByte( PWRCON, 0x0 ) |
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156 | SetExRegWord( CLKPRS, 0x17) # 0x13 for 1.19318 MHz. 0x17 for 1MHz. |
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157 | |
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158 | /************************************************************** |
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159 | * Initialize the Pin Configurations |
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160 | *************************************************************/ |
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161 | |
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162 | /* |
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163 | * Initialize I/O port 1 for: |
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164 | * PIN 0 = 1, DCD0# to package pin |
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165 | * PIN 1 = 1, RTS0# to package pin |
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166 | * PIN 2 = 1, DTR0# to package pin |
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167 | * PIN 3 = 1, DSR0# to package pin |
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168 | * PIN 4 = 1, RI0# to package pin |
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169 | * PIN 5 = 0, Outport (FLASH Vpp Enable, 0=Enable 1=Disable) |
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170 | * PIN 6 = 0, Outport (P16_HOLD to 386ex option header JP7 pin 5) |
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171 | * PIN 7 = 0, Outport (P17_HOLD to 386ex option header JP7 pin 3) |
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172 | */ |
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173 | |
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174 | SYM(InitPort1): |
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175 | SetExRegByte( P1LTC , 0xff ) |
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176 | SetExRegByte( P1DIR , 0x0 ) |
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177 | SetExRegByte( P1CFG , 0x1f) |
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178 | |
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179 | /* |
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180 | * Initialize I/O port 2 for: |
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181 | * PIN 0 = 0, Outport (P20_CS0# to 386ex option header JP7 pin 11) |
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182 | * PIN 1 = 0, Outport (P21_CS1# to 386ex option header JP7 pin 9) |
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183 | * PIN 2 = 1, CS2# (SMRAM) If not using CS2 can be configured as.? |
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184 | * PIN 3 = 0, Outport ( no connect ) |
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185 | * PIN 4 = 1, CS#4 (DRAM) |
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186 | * PIN 5 = 1, RXD0 input. See not for I/0 port 1 pins 1-4 |
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187 | * PIN 6 = 1, TXD0 output. |
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188 | * PIN 7 = 1, CTS0# input. |
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189 | */ |
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190 | |
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191 | SYM(InitPort2): |
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192 | SetExRegByte( P2LTC , 0xff ) |
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193 | SetExRegByte( P2DIR , 0x0 ) |
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194 | SetExRegByte( P2CFG , 0xfe) |
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195 | |
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196 | /* |
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197 | * Initialize I/O port 3 P3CFG |
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198 | * PIN 0 = 1, TMROUT0 to package pin |
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199 | * PIN 1 = 0, (TMROUT1 to 386ex option header JP7 pin 23) |
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200 | * PIN 2 = 0, INT0 (IR1) disabled, (P3.2 out to JP7 pin 21) |
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201 | * PIN 3 = 0, INT1 (IR5) disbled (P3.3 to option header JP7 pin 19) |
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202 | * PIN 4 = 0, INT2 (IR6) disbled (P3.4 to option header JP7 pin 17) |
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203 | * PIN 5 = 0, INT2 (IR7) disabled (P3.5 to 386ex header JP7 pin 15) |
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204 | * PIN 6 = 0, Inport (Debugger Break P3.6/PWRD to package pin ) |
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205 | * P3.6 selected |
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206 | * PIN 7 = 0, COMCLK output disabled, 1.8432 Mhz OSC1 oscillator. |
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207 | * ( Debbugger uses COMCLK as the clocking source ) |
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208 | * P3.7 connected to package pin. |
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209 | */ |
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210 | |
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211 | SYM(InitPort3): |
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212 | SetExRegByte( P3LTC , 0xff ) |
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213 | SetExRegByte( P3DIR , 0x41 ) |
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214 | SetExRegByte( P3CFG , 0x09 ) # can check TMROUT0 |
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215 | /* |
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216 | * Initialize Peripheral Pin Configurations: |
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217 | * PIN 0 = 1, RTS1# to package pin |
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218 | * PIN 1 = 1, DTR1# to package pin |
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219 | * PIN 2 = 1, TXD1 out to package pin |
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220 | * PIN 3 = 0, EOP#/TC |
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221 | * PIN 4 = 0, DACK0# |
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222 | * PIN 5 = 1, Timer2 |
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223 | * PIN 6 = 0, 0 => CS6# connected to package pin |
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224 | * PIN 7 = 0, Don't care |
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225 | */ |
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226 | |
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227 | SYM(InitPeriph): |
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228 | SetExRegByte( PINCFG , 0x24) |
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229 | |
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230 | /* |
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231 | * Initialize the Asynchronous Serial Ports: |
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232 | * BIT 7 = 1, Internal SIO1 modem signals |
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233 | * BIT 6 = 1, Internal SIO0 modem signals |
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234 | * BIT 2 = 0, PSCLK for SSIO clock |
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235 | * BIT 1 = 1, SERCLK for SIO1 clock |
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236 | * BIT 0 = 1, SERCLK for SIO0 clock |
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237 | */ |
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238 | |
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239 | SYM(InitSIO): |
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240 | SetExRegByte( SIOCFG, 0xC3 ) # SIOn clocked internally |
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241 | |
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242 | SetExRegByte( LCR0, 0x80 ) # latch DLL0, DLH0 |
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243 | SetExRegByte( DLL0, 0x51 ) # 0x51 sets to 9600 baud 0x7 -> 115,200 |
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244 | SetExRegByte( DLH0, 0x00 ) # 0x145 is 2400 baud |
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245 | SetExRegByte( LCR0, 0x03 ) # enable r/w buffers, IER0 accessible |
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246 | # mode 8-n-1 |
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247 | SetExRegByte( IER0, 0x00 ) # was 0x0f All interrupts detected |
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248 | |
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249 | SetExRegByte( LCR1, 0x80 ) # latch DLL0, DLH0 |
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250 | SetExRegByte( DLL1, 0x51 ) # 0x51 set to 9600 baud, 0x7 = 115200 |
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251 | SetExRegByte( DLH1, 0x00 ) # 0x145 is 2400 baud |
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252 | SetExRegByte( LCR1, 0x03 ) # enable r/w buffers, IER1 accessible |
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253 | # reg 8-n-1 |
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254 | SetExRegByte( IER1, 0x00 ) # was 0x0f - All interrupts detected |
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255 | |
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256 | SYM(InitMCR): |
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257 | /* |
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258 | * Initialize Timer for: |
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259 | * BIT 7 = 1, Timer clocks disabled |
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260 | * BIT 6 = 0, Reserved |
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261 | * BIT 5 = 1, TMRCLK2 instead of Vcc to Gate2 |
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262 | * BIT 4 = 0, PSCLK to CLK2 |
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263 | * BIT 3 = 1, TMRCLK1 instead of Vcc to Gate1 |
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264 | * BIT 2 = 0, PSCLK to Gate1 |
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265 | * BIT 1 = 0, Vcc to Gate0 |
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266 | * BIT 0 = 0, PSCLK to Gate0 |
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267 | */ |
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268 | |
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269 | SYM(InitTimer): |
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270 | SetExRegByte(TMRCFG , 0x80 ) # All counters disabled, Gates 0,1 |
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271 | # and 2 are set to Vcc |
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272 | |
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273 | SetExRegByte(TMRCON , 0x34 ) # prepare to write counter 0 LSB,MSB |
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274 | SetExRegByte(TMR0 , 0x00 ) # sfa |
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275 | SetExRegByte(TMR0 , 0x00 ) # sfa |
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276 | |
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277 | |
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278 | SetExRegByte(TMRCON , 0x70 ) # mode 0 disables on Gate= Vcc |
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279 | SetExRegByte(TMR1 , 0x00 ) # sfa |
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280 | SetExRegByte(TMR1 , 0x00 ) # sfa |
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281 | |
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282 | SetExRegByte(TMRCON , 0xB0 ) # mode 0 disables on gate =Vcc |
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283 | SetExRegByte(TMR2 , 0x00 ) # |
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284 | SetExRegByte(TMR2 , 0x00 ) # |
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285 | |
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286 | SetExRegByte(TMRCFG , 0x80 ) # Enable = 0x00 |
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287 | |
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288 | /* |
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289 | * Initialize the DMACFG register for: |
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290 | * BIT 7 = 1 , Disable DACK#1 |
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291 | * BITs 6:4 = 100, TMROUT2 connected to DRQ1 |
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292 | * BIT 3 = 1 , Disable DACK0# |
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293 | * BIT 2:0 = 000, Pin is connected to DRQ0 |
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294 | */ |
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295 | |
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296 | SetExRegByte(DMACFG , 0xC0 ) |
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297 | SetExRegByte(DMACMD1, 0x00 ) # disable both DMA channels |
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298 | SetExRegByte(DMAMOD1, 0x40 ) |
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299 | /* |
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300 | * Initialize the INTCFG register for: |
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301 | * BIT 7 = 0, 8259 cascade disabled |
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302 | * BIT 3 = 0, SLAVE IR6 connected to Vss |
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303 | * BIT 2 = 0, SLAVE IR5 connected to Vss |
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304 | * BIT 1 = 0, SLAVE IR1 connected to SSIOINT |
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305 | * BIT 0 = 0, SLAVE IR0 connected to Vss |
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306 | */ |
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307 | |
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308 | SYM(InitInt): |
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309 | |
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310 | cli # ! |
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311 | |
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312 | SetExRegByte(ICW1S , 0x11 ) # EDGE TRIGGERED |
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313 | SetExRegByte(ICW2S , 0x28 ) # Slave base vector after Master |
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314 | SetExRegByte(ICW3S , 0x02 ) # slave cascaded to IR2 on master |
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315 | SetExRegByte(ICW4S , 0x01 ) # must be 0x01 |
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316 | |
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317 | SetExRegByte(ICW1M , 0x11 ) # edge triggered |
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318 | SetExRegByte(ICW2M , 0x20 ) # base vector starts at byte 32 |
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319 | SetExRegByte(ICW3M , 0x04) # IR2 is cascaded internally |
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320 | SetExRegByte(ICW4M , 0x01 ) # idem |
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321 | |
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322 | SetExRegByte(OCW1M , 0xde ) # IR0 only = 0xfe. for IR5 and IR0 active use 0xde |
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323 | SetExRegByte(INTCFG , 0x00 ) |
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324 | |
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325 | movw $0xFFFB, SYM(i8259s_cache) /* set up same values in cache */ |
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326 | |
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327 | SYM(SetCS4): |
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328 | SetExRegWord(CS4ADL , 0x702) #Configure chip select 4 |
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329 | SetExRegWord(CS4ADH , 0x00) |
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330 | SetExRegWord(CS4MSKH, 0x03F) |
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331 | SetExRegWord(CS4MSKL, 0xFC01) |
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332 | |
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333 | SYM(SetUCS1): |
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334 | SetExRegWord(UCSADL , 0x0304) # 512K block starting at 0x80000 until 0x3f80000 |
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335 | SetExRegWord(UCSADH , 0x03F8) |
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336 | SetExRegWord(UCSMSKH, 0x03F7) |
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337 | SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select |
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338 | |
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339 | /****************************************************** |
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340 | * The GDT must be in RAM since it must be writeable, |
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341 | * So, move the whole data section down. |
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342 | ********************************************************/ |
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343 | |
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344 | movw $ _ram_data_offset , di |
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345 | movw $ _ram_data_segment, cx |
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346 | mov cx , es |
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347 | |
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348 | movw $ _data_size , cx |
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349 | movw $ _rom_data_segment, ax |
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350 | movw $ _rom_data_offset , si |
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351 | mov ax , ds |
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352 | |
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353 | repne |
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354 | movsb |
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355 | |
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356 | /***************************** |
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357 | * Load the Global Descriptor |
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358 | * Table Register |
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359 | ****************************/ |
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360 | |
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361 | #ifdef NEW_GAS |
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362 | data32 |
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363 | addr32 |
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364 | #endif |
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365 | lgdt SYM(GDTR) # location of GDT |
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366 | |
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367 | |
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368 | SYM(SetUCS): |
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369 | SetExRegWord(UCSADL, 0x0702) # now 512K starting at 0x3f80000. |
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370 | SetExRegWord(UCSADH, 0x03f8) |
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371 | SetExRegWord(UCSMSKH, 0x0007) |
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372 | SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select |
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373 | |
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374 | /*************************** |
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375 | * Switch to Protected Mode |
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376 | ***************************/ |
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377 | mov cr0, eax |
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378 | orw $0x1, ax |
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379 | mov eax, cr0 |
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380 | |
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381 | /************************** |
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382 | * Flush prefetch queue, |
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383 | * and load CS selector |
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384 | *********************/ |
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385 | |
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386 | ljmpl $ GDT_CODE_PTR , $ SYM(_load_segment_registers) # sets the code selector |
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387 | |
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388 | /* |
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389 | * Load the segment registers |
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390 | */ |
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391 | SYM(_load_segment_registers): |
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392 | .code32 |
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393 | pLOAD_SEGMENT( GDT_DATA_PTR, fs) |
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394 | pLOAD_SEGMENT( GDT_DATA_PTR, gs) |
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395 | pLOAD_SEGMENT( GDT_DATA_PTR, ss) |
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396 | pLOAD_SEGMENT( GDT_DATA_PTR, ds) |
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397 | pLOAD_SEGMENT( GDT_DATA_PTR, es) |
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398 | |
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399 | /* |
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400 | * Set up the stack |
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401 | */ |
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402 | |
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403 | SYM(lidtr): |
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404 | lidt SYM(IDTR) |
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405 | |
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406 | SYM (_establish_stack): |
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407 | movl $end, eax # stack starts right after bss |
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408 | movl $stack_origin, esp # this is the high starting address |
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409 | movl $stack_origin, ebp |
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410 | /* |
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411 | * Zero out the BSS segment |
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412 | */ |
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413 | SYM (zero_bss): |
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414 | cld # make direction flag count up |
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415 | movl $ SYM (end),ecx # find end of .bss |
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416 | movl $ SYM (_bss_start),edi # edi = beginning of .bss |
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417 | subl edi,ecx # ecx = size of .bss in bytes |
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418 | shrl ecx # size of .bss in longs |
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419 | shrl ecx |
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420 | xorl eax,eax # value to clear out memory |
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421 | repne # while ecx != 0 |
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422 | stosl # clear a long in the bss |
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423 | |
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424 | /* |
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425 | * Transfer control to User's Board Support Package |
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426 | */ |
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427 | pushl $0 # environp |
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428 | pushl $0 # argv |
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429 | pushl $0 # argc |
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430 | call SYM(boot_card) |
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431 | addl $12,esp |
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432 | |
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433 | cli # stops interrupts from being processed after hlt! |
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434 | hlt # shutdown |
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435 | |
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436 | END |
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437 | |
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