[33442772] | 1 | /* |
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| 2 | * This file is the main boot and configuration file for the i386ex. It is |
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| 3 | * solely responsible for initializing the internal register set to reflect |
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| 4 | * the proper board configuration. This version is the "generic" i386ex |
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| 5 | * startup: |
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| 6 | * |
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| 7 | * 1) 512K flask ROM @3f80000 |
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| 8 | * 2) 1 Mb RAM @ 0x0 |
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| 9 | * 3) Timer0 used as RTEMS clock ticker, 1 msec tick rate. |
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| 10 | * 4) READY# is generated by CPU |
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| 11 | * |
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| 12 | * The file is a multi-section file, with sections as follows: |
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| 13 | * 1) interrupt gates, in section "ints" |
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| 14 | * 2) interrupt descriptor table, in section "idt" |
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| 15 | * 3) global descriptor table, in section "gdt" |
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| 16 | * 4) reset in section "reset" |
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| 17 | * 5) and initial boot code in section " initial" |
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| 18 | * |
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| 19 | * Submitted by: |
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| 20 | * |
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| 21 | * Erik Ivanenko |
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| 22 | * University of Toronto |
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| 23 | * erik.ivanenko@utoronto.ca |
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| 24 | * |
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| 25 | * The license and distribution terms for this file may be |
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| 26 | * found in the file LICENSE in this distribution or at |
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| 27 | * http://www.OARcorp.com/rtems/license.html. |
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| 28 | * |
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| 29 | * $Id$ |
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[04bc5d9] | 30 | |
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| 31 | |
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| 32 | changes: |
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| 33 | SetExRegByte(ICW3S , 0x02 ) # MUST be 0x02 according to intel |
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| 34 | SetExRegByte(ICW3M , 0x04 ) # IR2 is cascaded internally: was 0x02 => IR1 is cascaded |
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| 35 | |
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[33442772] | 36 | */ |
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| 37 | |
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| 38 | #include "asm.h" |
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| 39 | #include "macros.inc" |
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| 40 | #include "80386ex.inc" |
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| 41 | |
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[bd8c8b2a] | 42 | /* |
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[42c0b9ee] | 43 | * NEW_GAS Needed for binutils 2.9.1.0.7 and higher |
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[bd8c8b2a] | 44 | */ |
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[33442772] | 45 | |
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[04bc5d9] | 46 | EXTERN (boot_card) /* exits to bspstart */ |
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| 47 | EXTERN (stack_start) /* defined in startup/linkcmds */ |
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| 48 | EXTERN (Clock_exit) |
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[33442772] | 49 | |
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| 50 | PUBLIC (Interrupt_descriptor_table) |
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[04bc5d9] | 51 | PUBLIC ( SYM(IDTR) ) |
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| 52 | PUBLIC( SYM(_initInternalRegisters) ) |
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| 53 | |
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| 54 | BEGIN_DATA |
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| 55 | SYM(IDTR): DESC3( SYM(Interrupt_descriptor_table), 0x07ff ); |
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| 56 | |
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| 57 | SYM(Interrupt_descriptor_table): /* Now in data section */ |
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| 58 | .rept 256 |
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| 59 | .word 0,0,0,0 |
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| 60 | .endr |
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| 61 | |
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[33442772] | 62 | END_DATA |
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| 63 | |
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| 64 | BEGIN_DATA |
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[04bc5d9] | 65 | PUBLIC (_Global_descriptor_table) |
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| 66 | |
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[33442772] | 67 | SYM(GDTR): DESC3( GDT_TABLE, 0x1f ); # one less than the size |
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| 68 | SYM (_Global_descriptor_table): |
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| 69 | SYM(GDT_TABLE): DESC2(0,0,0,0,0,0); |
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| 70 | SYM(GDT_ALIAS): DESC2(32,0x1000,0x0,0x93,0,0x0); |
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| 71 | SYM(GDT_CODE): DESC2(0xffff,0,0x0,0x9B,0xDF,0x00); |
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| 72 | SYM(GDT_DATA): DESC2(0xffff,0,0x0,0x92,0xDF,0x00); # was CF |
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| 73 | SYM(GDT_END): |
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| 74 | |
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| 75 | END_DATA |
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| 76 | |
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| 77 | |
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| 78 | /* This section is the section that is used by the interrupt |
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| 79 | descriptor table. It is used to provide the IDT with the |
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| 80 | correct vector offsets. It is for symbol definition only. |
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| 81 | */ |
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| 82 | |
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| 83 | |
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| 84 | .section .reset |
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| 85 | |
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| 86 | PUBLIC ( SYM(reset) ) |
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[04bc5d9] | 87 | SYM(reset): |
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[33442772] | 88 | nop |
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| 89 | cli |
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| 90 | jmp SYM(_initInternalRegisters) /* different section in this file */ |
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| 91 | .code32 /* in case this section moves */ |
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| 92 | nop /* required by CHIP LAB to pad out size */ |
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| 93 | nop |
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| 94 | nop |
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| 95 | nop |
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| 96 | nop |
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| 97 | |
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[04bc5d9] | 98 | |
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| 99 | |
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| 100 | .section .initial |
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[ddd22e5] | 101 | nop /* nops required to correct 32 bit jmp relative */ |
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| 102 | nop /* offset from .reset section */ |
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[04bc5d9] | 103 | |
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[33442772] | 104 | /* |
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| 105 | * Enable access to peripheral register at expanded I/O addresses |
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| 106 | */ |
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| 107 | SYM(_initInternalRegisters): |
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[bd8c8b2a] | 108 | .code16 |
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[33442772] | 109 | movw $0x8000 , ax |
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| 110 | outb al , $REMAPCFGH |
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| 111 | xchg al , ah |
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| 112 | outb al,$REMAPCFGL |
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| 113 | outw ax, $REMAPCFG ; |
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| 114 | |
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| 115 | |
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| 116 | /* |
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| 117 | * Configure operation of the A20 Address Line |
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| 118 | */ |
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| 119 | SYM(A20): |
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| 120 | movw $PORT92 , dx |
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| 121 | |
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| 122 | inb dx , al # clear A20 port reset |
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| 123 | andb $0xfe , al # b0 Fast Reset(0)=disabled,(1)=reset triggered |
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| 124 | orb $0x02 , al # Bit 1 Fast A20 = 0 (always 0) else enabled. |
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| 125 | outb al , dx |
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| 126 | |
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[04bc5d9] | 127 | SYM(Watchdog): |
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| 128 | movw $WDTSTATUS , dx # address the WDT status port |
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| 129 | inb dx , al # get the WDT status |
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| 130 | orb $0x01 , al # set the CLKDIS bit |
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| 131 | outb al , dx # disable the clock to the WDT |
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[33442772] | 132 | |
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| 133 | /* |
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| 134 | * Initialize Refresh Control Unit for: |
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| 135 | * Refresh Address = 0x0000 |
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| 136 | |
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| 137 | * Refresh gate between rows is 15.6 uSec |
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| 138 | * Using a CLK2 frequency of 50Mhz ( 25Mhz CPU ) |
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| 139 | * The refresh unit is enabled |
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| 140 | * The refresh pin is not used. |
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| 141 | */ |
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| 142 | |
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| 143 | SYM(InitRCU): |
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| 144 | SetExRegWord( RFSCIR , 390) # refresh interval was 390, tried 312 |
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| 145 | SetExRegWord( RFSBAD , 0x0) # base address |
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| 146 | SetExRegWord( RFSADD , 0x0) # address register |
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| 147 | SetExRegWord( RFSCON , 0x8000) # enable bit |
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| 148 | |
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| 149 | /* |
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| 150 | * Initialize clock and power mgmt unit for: |
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| 151 | * Clock Frequency = 50 Mhz |
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[479c86dd] | 152 | * Prescaled clock output = 1 Mhz |
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[33442772] | 153 | * Normal halt instructions |
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| 154 | */ |
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| 155 | |
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| 156 | SYM(InitClk): |
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| 157 | SetExRegByte( PWRCON, 0x0 ) |
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[479c86dd] | 158 | SetExRegWord( CLKPRS, 0x17) # 0x13 for 1.19318 MHz. 0x17 for 1MHz. |
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[33442772] | 159 | |
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| 160 | /************************************************************** |
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| 161 | * Initialize the Pin Configurations |
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| 162 | *************************************************************/ |
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| 163 | |
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| 164 | /* |
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| 165 | * Initialize I/O port 1 for: |
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| 166 | * PIN 0 = 1, DCD0# to package pin |
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| 167 | * PIN 1 = 1, RTS0# to package pin |
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| 168 | * PIN 2 = 1, DTR0# to package pin |
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| 169 | * PIN 3 = 1, DSR0# to package pin |
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| 170 | * PIN 4 = 1, RI0# to package pin |
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| 171 | * PIN 5 = 0, Outport (FLASH Vpp Enable, 0=Enable 1=Disable) |
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| 172 | * PIN 6 = 0, Outport (P16_HOLD to 386ex option header JP7 pin 5) |
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| 173 | * PIN 7 = 0, Outport (P17_HOLD to 386ex option header JP7 pin 3) |
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| 174 | */ |
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| 175 | |
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| 176 | SYM(InitPort1): |
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| 177 | SetExRegByte( P1LTC , 0xff ) |
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| 178 | SetExRegByte( P1DIR , 0x0 ) |
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| 179 | SetExRegByte( P1CFG , 0x1f) |
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| 180 | |
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| 181 | /* |
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| 182 | * Initialize I/O port 2 for: |
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| 183 | * PIN 0 = 0, Outport (P20_CS0# to 386ex option header JP7 pin 11) |
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| 184 | * PIN 1 = 0, Outport (P21_CS1# to 386ex option header JP7 pin 9) |
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| 185 | * PIN 2 = 1, CS2# (SMRAM) If not using CS2 can be configured as.? |
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| 186 | * PIN 3 = 0, Outport ( no connect ) |
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| 187 | * PIN 4 = 1, CS#4 (DRAM) |
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| 188 | * PIN 5 = 1, RXD0 input. See not for I/0 port 1 pins 1-4 |
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| 189 | * PIN 6 = 1, TXD0 output. |
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| 190 | * PIN 7 = 1, CTS0# input. |
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| 191 | */ |
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| 192 | |
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| 193 | SYM(InitPort2): |
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| 194 | SetExRegByte( P2LTC , 0xff ) |
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| 195 | SetExRegByte( P2DIR , 0x0 ) |
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| 196 | SetExRegByte( P2CFG , 0xfe) |
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| 197 | |
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| 198 | /* |
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| 199 | * Initialize I/O port 3 P3CFG |
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| 200 | * PIN 0 = 1, TMROUT0 to package pin |
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| 201 | * PIN 1 = 0, (TMROUT1 to 386ex option header JP7 pin 23) |
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| 202 | * PIN 2 = 0, INT0 (IR1) disabled, (P3.2 out to JP7 pin 21) |
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| 203 | * PIN 3 = 0, INT1 (IR5) disbled (P3.3 to option header JP7 pin 19) |
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| 204 | * PIN 4 = 0, INT2 (IR6) disbled (P3.4 to option header JP7 pin 17) |
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| 205 | * PIN 5 = 0, INT2 (IR7) disabled (P3.5 to 386ex header JP7 pin 15) |
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| 206 | * PIN 6 = 0, Inport (Debugger Break P3.6/PWRD to package pin ) |
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| 207 | * P3.6 selected |
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| 208 | * PIN 7 = 0, COMCLK output disabled, 1.8432 Mhz OSC1 oscillator. |
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| 209 | * ( Debbugger uses COMCLK as the clocking source ) |
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| 210 | * P3.7 connected to package pin. |
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| 211 | */ |
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| 212 | |
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| 213 | SYM(InitPort3): |
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| 214 | SetExRegByte( P3LTC , 0xff ) |
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| 215 | SetExRegByte( P3DIR , 0x41 ) |
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| 216 | SetExRegByte( P3CFG , 0x09 ) # can check TMROUT0 |
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| 217 | /* |
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| 218 | * Initialize Peripheral Pin Configurations: |
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| 219 | * PIN 0 = 1, RTS1# to package pin |
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| 220 | * PIN 1 = 1, DTR1# to package pin |
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| 221 | * PIN 2 = 1, TXD1 out to package pin |
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| 222 | * PIN 3 = 0, EOP#/TC |
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| 223 | * PIN 4 = 0, DACK0# |
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| 224 | * PIN 5 = 1, Timer2 |
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| 225 | * PIN 6 = 0, 0 => CS6# connected to package pin |
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| 226 | * PIN 7 = 0, Don't care |
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| 227 | */ |
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| 228 | |
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| 229 | SYM(InitPeriph): |
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| 230 | SetExRegByte( PINCFG , 0x24) |
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| 231 | |
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| 232 | /* |
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| 233 | * Initialize the Asynchronous Serial Ports: |
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| 234 | * BIT 7 = 1, Internal SIO1 modem signals |
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| 235 | * BIT 6 = 1, Internal SIO0 modem signals |
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| 236 | * BIT 2 = 0, PSCLK for SSIO clock |
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| 237 | * BIT 1 = 1, SERCLK for SIO1 clock |
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| 238 | * BIT 0 = 1, SERCLK for SIO0 clock |
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| 239 | */ |
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| 240 | |
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| 241 | SYM(InitSIO): |
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| 242 | SetExRegByte( SIOCFG, 0xC3 ) # SIOn clocked internally |
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| 243 | |
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| 244 | SetExRegByte( LCR0, 0x80 ) # latch DLL0, DLH0 |
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| 245 | SetExRegByte( DLL0, 0x51 ) # 0x51 sets to 9600 baud 0x7 -> 115,200 |
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| 246 | SetExRegByte( DLH0, 0x00 ) # 0x145 is 2400 baud |
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| 247 | SetExRegByte( LCR0, 0x03 ) # enable r/w buffers, IER0 accessible |
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| 248 | # mode 8-n-1 |
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| 249 | SetExRegByte( IER0, 0x00 ) # was 0x0f All interrupts detected |
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| 250 | |
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| 251 | SetExRegByte( LCR1, 0x80 ) # latch DLL0, DLH0 |
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| 252 | SetExRegByte( DLL1, 0x51 ) # 0x51 set to 9600 baud, 0x7 = 115200 |
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| 253 | SetExRegByte( DLH1, 0x00 ) # 0x145 is 2400 baud |
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| 254 | SetExRegByte( LCR1, 0x03 ) # enable r/w buffers, IER1 accessible |
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| 255 | # reg 8-n-1 |
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| 256 | SetExRegByte( IER1, 0x00 ) # was 0x0f - All interrupts detected |
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| 257 | |
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| 258 | SYM(InitMCR): |
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| 259 | /* |
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| 260 | * Initialize Timer for: |
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| 261 | * BIT 7 = 1, Timer clocks disabled |
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| 262 | * BIT 6 = 0, Reserved |
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| 263 | * BIT 5 = 1, TMRCLK2 instead of Vcc to Gate2 |
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| 264 | * BIT 4 = 0, PSCLK to CLK2 |
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| 265 | * BIT 3 = 1, TMRCLK1 instead of Vcc to Gate1 |
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| 266 | * BIT 2 = 0, PSCLK to Gate1 |
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| 267 | * BIT 1 = 0, Vcc to Gate0 |
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| 268 | * BIT 0 = 0, PSCLK to Gate0 |
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| 269 | */ |
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| 270 | |
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| 271 | SYM(InitTimer): |
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| 272 | SetExRegByte(TMRCFG , 0x80 ) # All counters disabled, Gates 0,1 |
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| 273 | # and 2 are set to Vcc |
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| 274 | |
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| 275 | SetExRegByte(TMRCON , 0x34 ) # prepare to write counter 0 LSB,MSB |
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[479c86dd] | 276 | SetExRegByte(TMR0 , 0x00 ) # sfa |
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| 277 | SetExRegByte(TMR0 , 0x00 ) # sfa |
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| 278 | |
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| 279 | |
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[33442772] | 280 | SetExRegByte(TMRCON , 0x70 ) # mode 0 disables on Gate= Vcc |
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| 281 | SetExRegByte(TMR1 , 0x00 ) # sfa |
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| 282 | SetExRegByte(TMR1 , 0x00 ) # sfa |
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| 283 | |
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| 284 | SetExRegByte(TMRCON , 0xB0 ) # mode 0 disables on gate =Vcc |
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| 285 | SetExRegByte(TMR2 , 0x00 ) # |
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[479c86dd] | 286 | SetExRegByte(TMR2 , 0x00 ) # |
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| 287 | |
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| 288 | SetExRegByte(TMRCFG , 0x80 ) # Enable = 0x00 |
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[33442772] | 289 | |
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| 290 | /* |
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| 291 | * Initialize the DMACFG register for: |
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| 292 | * BIT 7 = 1 , Disable DACK#1 |
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| 293 | * BITs 6:4 = 100, TMROUT2 connected to DRQ1 |
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| 294 | * BIT 3 = 1 , Disable DACK0# |
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| 295 | * BIT 2:0 = 000, Pin is connected to DRQ0 |
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| 296 | */ |
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| 297 | |
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| 298 | SetExRegByte(DMACFG , 0xC0 ) |
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| 299 | SetExRegByte(DMACMD1, 0x00 ) # disable both DMA channels |
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| 300 | SetExRegByte(DMAMOD1, 0x40 ) |
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| 301 | /* |
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| 302 | * Initialize the INTCFG register for: |
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| 303 | * BIT 7 = 0, 8259 cascade disabled |
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| 304 | * BIT 3 = 0, SLAVE IR6 connected to Vss |
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| 305 | * BIT 2 = 0, SLAVE IR5 connected to Vss |
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| 306 | * BIT 1 = 0, SLAVE IR1 connected to SSIOINT |
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| 307 | * BIT 0 = 0, SLAVE IR0 connected to Vss |
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| 308 | */ |
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| 309 | |
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| 310 | SYM(InitInt): |
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| 311 | |
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| 312 | cli # ! |
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| 313 | |
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| 314 | SetExRegByte(ICW1S , 0x11 ) # EDGE TRIGGERED |
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| 315 | SetExRegByte(ICW2S , 0x28 ) # Slave base vector after Master |
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[04bc5d9] | 316 | SetExRegByte(ICW3S , 0x02 ) # slave cascaded to IR2 on master |
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[33442772] | 317 | SetExRegByte(ICW4S , 0x01 ) # must be 0x01 |
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| 318 | |
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| 319 | SetExRegByte(ICW1M , 0x11 ) # edge triggered |
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[04bc5d9] | 320 | SetExRegByte(ICW2M , 0x20 ) # base vector starts at byte 32 |
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| 321 | SetExRegByte(ICW3M , 0x04) # IR2 is cascaded internally |
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[bd8c8b2a] | 322 | SetExRegByte(ICW4M , 0x01 ) # idem |
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[33442772] | 323 | |
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| 324 | SetExRegByte(OCW1M , 0xde ) # IR0 only = 0xfe. for IR5 and IR0 active use 0xde |
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| 325 | SetExRegByte(INTCFG , 0x00 ) |
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| 326 | |
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[04bc5d9] | 327 | movw $0xFFFB, SYM(i8259s_cache) /* set up same values in cache */ |
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| 328 | |
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[33442772] | 329 | SYM(SetCS4): |
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| 330 | SetExRegWord(CS4ADL , 0x702) #Configure chip select 4 |
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| 331 | SetExRegWord(CS4ADH , 0x00) |
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| 332 | SetExRegWord(CS4MSKH, 0x03F) |
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| 333 | SetExRegWord(CS4MSKL, 0xFC01) |
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| 334 | |
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| 335 | SYM(SetUCS1): |
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| 336 | SetExRegWord(UCSADL , 0x0304) # 512K block starting at 0x80000 until 0x3f80000 |
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| 337 | SetExRegWord(UCSADH , 0x03F8) |
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| 338 | SetExRegWord(UCSMSKH, 0x03F7) |
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| 339 | SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select |
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| 340 | |
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[04bc5d9] | 341 | /****************************************************** |
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| 342 | * The GDT must be in RAM since it must be writeable, |
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| 343 | * So, move the whole data section down. |
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| 344 | ********************************************************/ |
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| 345 | |
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| 346 | movw $ _ram_data_offset , di |
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| 347 | movw $ _ram_data_segment, cx |
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| 348 | mov cx , es |
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| 349 | |
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| 350 | movw $ _data_size , cx |
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| 351 | movw $ _rom_data_segment, ax |
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| 352 | movw $ _rom_data_offset , si |
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| 353 | mov ax , ds |
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| 354 | |
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[33442772] | 355 | repne |
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| 356 | movsb |
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| 357 | |
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| 358 | /***************************** |
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| 359 | * Load the Global Descriptor |
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| 360 | * Table Register |
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| 361 | ****************************/ |
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| 362 | |
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[42c0b9ee] | 363 | #ifdef NEW_GAS |
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[bd8c8b2a] | 364 | data32 |
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| 365 | addr32 |
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| 366 | #endif |
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[04bc5d9] | 367 | lgdt SYM(GDTR) # location of GDT |
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[33442772] | 368 | |
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| 369 | |
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| 370 | SYM(SetUCS): |
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[04bc5d9] | 371 | SetExRegWord(UCSADL, 0x0702) # now 512K starting at 0x3f80000. |
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[33442772] | 372 | SetExRegWord(UCSADH, 0x03f8) |
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| 373 | SetExRegWord(UCSMSKH, 0x0007) |
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| 374 | SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select |
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| 375 | |
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| 376 | /*************************** |
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| 377 | * Switch to Protected Mode |
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| 378 | ***************************/ |
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[bd8c8b2a] | 379 | mov cr0, eax |
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[33442772] | 380 | orw $0x1, ax |
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[bd8c8b2a] | 381 | mov eax, cr0 |
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[33442772] | 382 | |
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| 383 | /************************** |
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| 384 | * Flush prefetch queue, |
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| 385 | * and load CS selector |
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| 386 | *********************/ |
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| 387 | |
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[04bc5d9] | 388 | ljmpl $ GDT_CODE_PTR , $ SYM(_load_segment_registers) # sets the code selector |
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| 389 | |
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[33442772] | 390 | /* |
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[32f3e34] | 391 | * Load the segment registers |
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[33442772] | 392 | */ |
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[04bc5d9] | 393 | SYM(_load_segment_registers): |
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[33442772] | 394 | .code32 |
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| 395 | pLOAD_SEGMENT( GDT_DATA_PTR, fs) |
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| 396 | pLOAD_SEGMENT( GDT_DATA_PTR, gs) |
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| 397 | pLOAD_SEGMENT( GDT_DATA_PTR, ss) |
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| 398 | pLOAD_SEGMENT( GDT_DATA_PTR, ds) |
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| 399 | pLOAD_SEGMENT( GDT_DATA_PTR, es) |
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| 400 | |
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| 401 | /* |
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| 402 | * Set up the stack |
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| 403 | */ |
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| 404 | |
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[04bc5d9] | 405 | SYM(lidtr): |
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| 406 | lidt SYM(IDTR) |
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| 407 | |
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[33442772] | 408 | SYM (_establish_stack): |
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| 409 | movl $end, eax # stack starts right after bss |
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| 410 | movl $stack_origin, esp # this is the high starting address |
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| 411 | movl $stack_origin, ebp |
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| 412 | /* |
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| 413 | * Zero out the BSS segment |
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| 414 | */ |
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| 415 | SYM (zero_bss): |
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| 416 | cld # make direction flag count up |
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| 417 | movl $ SYM (end),ecx # find end of .bss |
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| 418 | movl $ SYM (_bss_start),edi # edi = beginning of .bss |
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| 419 | subl edi,ecx # ecx = size of .bss in bytes |
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| 420 | shrl ecx # size of .bss in longs |
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| 421 | shrl ecx |
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| 422 | xorl eax,eax # value to clear out memory |
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| 423 | repne # while ecx != 0 |
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| 424 | stosl # clear a long in the bss |
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| 425 | |
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| 426 | /* |
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| 427 | * Transfer control to User's Board Support Package |
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| 428 | */ |
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| 429 | pushl $0 # environp |
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| 430 | pushl $0 # argv |
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| 431 | pushl $0 # argc |
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[04bc5d9] | 432 | call SYM(boot_card) |
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[33442772] | 433 | addl $12,esp |
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[32f3e34] | 434 | |
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| 435 | cli # stops interrupts from being processed after hlt! |
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| 436 | hlt # shutdown |
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[33442772] | 437 | |
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| 438 | END |
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[04bc5d9] | 439 | |
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