[33442772] | 1 | /* |
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| 2 | * This file is the main boot and configuration file for the i386ex. It is |
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| 3 | * solely responsible for initializing the internal register set to reflect |
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| 4 | * the proper board configuration. This version is the "generic" i386ex |
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[6128a4a] | 5 | * startup: |
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[33442772] | 6 | * |
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| 7 | * 1) 512K flask ROM @3f80000 |
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| 8 | * 2) 1 Mb RAM @ 0x0 |
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| 9 | * 3) Timer0 used as RTEMS clock ticker, 1 msec tick rate. |
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| 10 | * 4) READY# is generated by CPU |
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| 11 | * |
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[6128a4a] | 12 | * The file is a multi-section file, with sections as follows: |
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[33442772] | 13 | * 1) interrupt gates, in section "ints" |
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| 14 | * 2) interrupt descriptor table, in section "idt" |
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| 15 | * 3) global descriptor table, in section "gdt" |
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| 16 | * 4) reset in section "reset" |
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| 17 | * 5) and initial boot code in section " initial" |
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| 18 | * |
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| 19 | * Submitted by: |
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| 20 | * |
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| 21 | * Erik Ivanenko |
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| 22 | * University of Toronto |
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| 23 | * erik.ivanenko@utoronto.ca |
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| 24 | * |
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| 25 | * The license and distribution terms for this file may be |
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| 26 | * found in the file LICENSE in this distribution or at |
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[6ff7e2c] | 27 | * http://www.rtems.com/license/LICENSE. |
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[33442772] | 28 | * |
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| 29 | * $Id$ |
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[04bc5d9] | 30 | |
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[6128a4a] | 31 | changes: |
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[04bc5d9] | 32 | SetExRegByte(ICW3S , 0x02 ) # MUST be 0x02 according to intel |
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| 33 | SetExRegByte(ICW3M , 0x04 ) # IR2 is cascaded internally: was 0x02 => IR1 is cascaded |
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[6128a4a] | 34 | |
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[33442772] | 35 | */ |
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| 36 | |
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[cc1426bb] | 37 | #include <rtems/asm.h> |
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[33442772] | 38 | #include "macros.inc" |
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| 39 | #include "80386ex.inc" |
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| 40 | |
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[bd8c8b2a] | 41 | /* |
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[42c0b9ee] | 42 | * NEW_GAS Needed for binutils 2.9.1.0.7 and higher |
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[6128a4a] | 43 | */ |
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[33442772] | 44 | |
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[6128a4a] | 45 | EXTERN (boot_card) /* exits to bspstart */ |
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[04bc5d9] | 46 | EXTERN (stack_start) /* defined in startup/linkcmds */ |
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| 47 | EXTERN (Clock_exit) |
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[33442772] | 48 | |
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| 49 | PUBLIC (Interrupt_descriptor_table) |
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[04bc5d9] | 50 | PUBLIC ( SYM(IDTR) ) |
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[f70598c7] | 51 | /* PUBLIC( SYM(_initInternalRegisters) ) */ |
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[6128a4a] | 52 | |
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| 53 | BEGIN_DATA |
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[04bc5d9] | 54 | SYM(IDTR): DESC3( SYM(Interrupt_descriptor_table), 0x07ff ); |
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[6128a4a] | 55 | |
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[04bc5d9] | 56 | SYM(Interrupt_descriptor_table): /* Now in data section */ |
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| 57 | .rept 256 |
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| 58 | .word 0,0,0,0 |
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| 59 | .endr |
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| 60 | |
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[6128a4a] | 61 | END_DATA |
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| 62 | |
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[33442772] | 63 | BEGIN_DATA |
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[04bc5d9] | 64 | PUBLIC (_Global_descriptor_table) |
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[6128a4a] | 65 | |
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[33442772] | 66 | SYM(GDTR): DESC3( GDT_TABLE, 0x1f ); # one less than the size |
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[6128a4a] | 67 | SYM (_Global_descriptor_table): |
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[33442772] | 68 | SYM(GDT_TABLE): DESC2(0,0,0,0,0,0); |
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[6128a4a] | 69 | SYM(GDT_ALIAS): DESC2(32,0x1000,0x0,0x93,0,0x0); |
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[33442772] | 70 | SYM(GDT_CODE): DESC2(0xffff,0,0x0,0x9B,0xDF,0x00); |
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| 71 | SYM(GDT_DATA): DESC2(0xffff,0,0x0,0x92,0xDF,0x00); # was CF |
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| 72 | SYM(GDT_END): |
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| 73 | |
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| 74 | END_DATA |
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[6128a4a] | 75 | |
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[33442772] | 76 | /* This section is the section that is used by the interrupt |
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| 77 | descriptor table. It is used to provide the IDT with the |
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| 78 | correct vector offsets. It is for symbol definition only. |
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| 79 | */ |
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[6128a4a] | 80 | |
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[f70598c7] | 81 | .code16 |
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[df49c60] | 82 | .section .reset, "ax" |
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[6128a4a] | 83 | PUBLIC ( SYM(reset) ) |
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[f70598c7] | 84 | SYM(reset): |
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[33442772] | 85 | nop |
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| 86 | cli |
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[6128a4a] | 87 | #ifdef NEW_GAS |
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[8be7bef] | 88 | data32 addr32 jmp SYM(_initInternalRegisters) /* different section in this file */ |
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| 89 | #else |
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[33442772] | 90 | jmp SYM(_initInternalRegisters) /* different section in this file */ |
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[6128a4a] | 91 | #endif |
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[f70598c7] | 92 | /* .code32 in case this section moves */ |
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[33442772] | 93 | nop /* required by CHIP LAB to pad out size */ |
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| 94 | nop |
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| 95 | nop |
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| 96 | nop |
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| 97 | nop |
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[f70598c7] | 98 | nop |
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| 99 | nop |
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| 100 | nop |
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| 101 | nop |
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| 102 | nop |
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| 103 | nop |
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[6128a4a] | 104 | |
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[df49c60] | 105 | .section .initial, "ax" |
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[f70598c7] | 106 | /* nop */ /* required for linker -- initial jump is to "label - 2" */ |
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[6128a4a] | 107 | /* nop */ /* ie. _initInternalRegisters -2 ( which now == .initial ) */ |
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[33442772] | 108 | /* |
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| 109 | * Enable access to peripheral register at expanded I/O addresses |
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| 110 | */ |
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[6128a4a] | 111 | SYM(_initInternalRegisters): |
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[f70598c7] | 112 | |
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| 113 | /* .code16 */ |
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[6128a4a] | 114 | movw $0x8000 , ax |
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[33442772] | 115 | outb al , $REMAPCFGH |
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| 116 | xchg al , ah |
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| 117 | outb al,$REMAPCFGL |
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| 118 | outw ax, $REMAPCFG ; |
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| 119 | /* |
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| 120 | * Configure operation of the A20 Address Line |
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[6128a4a] | 121 | */ |
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[33442772] | 122 | SYM(A20): |
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| 123 | movw $PORT92 , dx |
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[6128a4a] | 124 | |
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[33442772] | 125 | inb dx , al # clear A20 port reset |
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| 126 | andb $0xfe , al # b0 Fast Reset(0)=disabled,(1)=reset triggered |
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| 127 | orb $0x02 , al # Bit 1 Fast A20 = 0 (always 0) else enabled. |
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| 128 | outb al , dx |
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| 129 | |
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[04bc5d9] | 130 | SYM(Watchdog): |
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| 131 | movw $WDTSTATUS , dx # address the WDT status port |
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| 132 | inb dx , al # get the WDT status |
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[6128a4a] | 133 | orb $0x01 , al # set the CLKDIS bit |
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[04bc5d9] | 134 | outb al , dx # disable the clock to the WDT |
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[33442772] | 135 | |
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| 136 | /* |
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[6128a4a] | 137 | * Initialize Refresh Control Unit for: |
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[33442772] | 138 | * Refresh Address = 0x0000 |
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| 139 | |
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| 140 | * Refresh gate between rows is 15.6 uSec |
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| 141 | * Using a CLK2 frequency of 50Mhz ( 25Mhz CPU ) |
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| 142 | * The refresh unit is enabled |
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| 143 | * The refresh pin is not used. |
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| 144 | */ |
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| 145 | |
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[6128a4a] | 146 | SYM(InitRCU): |
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[33442772] | 147 | SetExRegWord( RFSCIR , 390) # refresh interval was 390, tried 312 |
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| 148 | SetExRegWord( RFSBAD , 0x0) # base address |
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| 149 | SetExRegWord( RFSADD , 0x0) # address register |
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| 150 | SetExRegWord( RFSCON , 0x8000) # enable bit |
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| 151 | |
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| 152 | /* |
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[6128a4a] | 153 | * Initialize clock and power mgmt unit for: |
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[33442772] | 154 | * Clock Frequency = 50 Mhz |
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[479c86dd] | 155 | * Prescaled clock output = 1 Mhz |
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[33442772] | 156 | * Normal halt instructions |
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| 157 | */ |
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[6128a4a] | 158 | |
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| 159 | SYM(InitClk): |
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[33442772] | 160 | SetExRegByte( PWRCON, 0x0 ) |
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[479c86dd] | 161 | SetExRegWord( CLKPRS, 0x17) # 0x13 for 1.19318 MHz. 0x17 for 1MHz. |
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[33442772] | 162 | |
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| 163 | /************************************************************** |
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| 164 | * Initialize the Pin Configurations |
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| 165 | *************************************************************/ |
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| 166 | |
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| 167 | /* |
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[6128a4a] | 168 | * Initialize I/O port 1 for: |
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[33442772] | 169 | * PIN 0 = 1, DCD0# to package pin |
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| 170 | * PIN 1 = 1, RTS0# to package pin |
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| 171 | * PIN 2 = 1, DTR0# to package pin |
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| 172 | * PIN 3 = 1, DSR0# to package pin |
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| 173 | * PIN 4 = 1, RI0# to package pin |
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| 174 | * PIN 5 = 0, Outport (FLASH Vpp Enable, 0=Enable 1=Disable) |
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| 175 | * PIN 6 = 0, Outport (P16_HOLD to 386ex option header JP7 pin 5) |
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| 176 | * PIN 7 = 0, Outport (P17_HOLD to 386ex option header JP7 pin 3) |
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| 177 | */ |
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| 178 | |
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[6128a4a] | 179 | SYM(InitPort1): |
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[33442772] | 180 | SetExRegByte( P1LTC , 0xff ) |
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| 181 | SetExRegByte( P1DIR , 0x0 ) |
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| 182 | SetExRegByte( P1CFG , 0x1f) |
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[6128a4a] | 183 | |
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[33442772] | 184 | /* |
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[6128a4a] | 185 | * Initialize I/O port 2 for: |
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| 186 | * PIN 0 = 0, Outport (P20_CS0# to 386ex option header JP7 pin 11) |
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| 187 | * PIN 1 = 0, Outport (P21_CS1# to 386ex option header JP7 pin 9) |
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[33442772] | 188 | * PIN 2 = 1, CS2# (SMRAM) If not using CS2 can be configured as.? |
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| 189 | * PIN 3 = 0, Outport ( no connect ) |
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| 190 | * PIN 4 = 1, CS#4 (DRAM) |
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| 191 | * PIN 5 = 1, RXD0 input. See not for I/0 port 1 pins 1-4 |
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| 192 | * PIN 6 = 1, TXD0 output. |
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| 193 | * PIN 7 = 1, CTS0# input. |
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| 194 | */ |
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[6128a4a] | 195 | |
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| 196 | SYM(InitPort2): |
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[33442772] | 197 | SetExRegByte( P2LTC , 0xff ) |
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| 198 | SetExRegByte( P2DIR , 0x0 ) |
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| 199 | SetExRegByte( P2CFG , 0xfe) |
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[6128a4a] | 200 | |
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[33442772] | 201 | /* |
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[6128a4a] | 202 | * Initialize I/O port 3 P3CFG |
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[33442772] | 203 | * PIN 0 = 1, TMROUT0 to package pin |
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[6128a4a] | 204 | * PIN 1 = 0, (TMROUT1 to 386ex option header JP7 pin 23) |
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| 205 | * PIN 2 = 0, INT0 (IR1) disabled, (P3.2 out to JP7 pin 21) |
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| 206 | * PIN 3 = 0, INT1 (IR5) disbled (P3.3 to option header JP7 pin 19) |
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| 207 | * PIN 4 = 0, INT2 (IR6) disbled (P3.4 to option header JP7 pin 17) |
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| 208 | * PIN 5 = 0, INT2 (IR7) disabled (P3.5 to 386ex header JP7 pin 15) |
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[33442772] | 209 | * PIN 6 = 0, Inport (Debugger Break P3.6/PWRD to package pin ) |
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| 210 | * P3.6 selected |
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| 211 | * PIN 7 = 0, COMCLK output disabled, 1.8432 Mhz OSC1 oscillator. |
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| 212 | * ( Debbugger uses COMCLK as the clocking source ) |
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| 213 | * P3.7 connected to package pin. |
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| 214 | */ |
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[6128a4a] | 215 | |
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| 216 | SYM(InitPort3): |
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[33442772] | 217 | SetExRegByte( P3LTC , 0xff ) |
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| 218 | SetExRegByte( P3DIR , 0x41 ) |
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| 219 | SetExRegByte( P3CFG , 0x09 ) # can check TMROUT0 |
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| 220 | /* |
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[6128a4a] | 221 | * Initialize Peripheral Pin Configurations: |
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| 222 | * PIN 0 = 1, RTS1# to package pin |
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[33442772] | 223 | * PIN 1 = 1, DTR1# to package pin |
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| 224 | * PIN 2 = 1, TXD1 out to package pin |
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| 225 | * PIN 3 = 0, EOP#/TC |
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| 226 | * PIN 4 = 0, DACK0# |
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| 227 | * PIN 5 = 1, Timer2 |
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| 228 | * PIN 6 = 0, 0 => CS6# connected to package pin |
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| 229 | * PIN 7 = 0, Don't care |
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| 230 | */ |
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[6128a4a] | 231 | |
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| 232 | SYM(InitPeriph): |
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| 233 | SetExRegByte( PINCFG , 0x24) |
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| 234 | |
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[33442772] | 235 | /* |
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[6128a4a] | 236 | * Initialize the Asynchronous Serial Ports: |
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[33442772] | 237 | * BIT 7 = 1, Internal SIO1 modem signals |
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| 238 | * BIT 6 = 1, Internal SIO0 modem signals |
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| 239 | * BIT 2 = 0, PSCLK for SSIO clock |
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[6128a4a] | 240 | * BIT 1 = 1, SERCLK for SIO1 clock |
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[33442772] | 241 | * BIT 0 = 1, SERCLK for SIO0 clock |
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| 242 | */ |
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| 243 | |
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[6128a4a] | 244 | SYM(InitSIO): |
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[33442772] | 245 | SetExRegByte( SIOCFG, 0xC3 ) # SIOn clocked internally |
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| 246 | |
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| 247 | SetExRegByte( LCR0, 0x80 ) # latch DLL0, DLH0 |
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[f70598c7] | 248 | SetExRegByte( DLL0, 0x51 ) # 0x51 sets to 9600 baud, 0x28=19.2k, 0x7 -> 115.2k |
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[33442772] | 249 | SetExRegByte( DLH0, 0x00 ) # 0x145 is 2400 baud |
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| 250 | SetExRegByte( LCR0, 0x03 ) # enable r/w buffers, IER0 accessible |
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| 251 | # mode 8-n-1 |
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| 252 | SetExRegByte( IER0, 0x00 ) # was 0x0f All interrupts detected |
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[6128a4a] | 253 | |
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| 254 | SetExRegByte( LCR1, 0x80 ) # latch DLL0, DLH0 |
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[33442772] | 255 | SetExRegByte( DLL1, 0x51 ) # 0x51 set to 9600 baud, 0x7 = 115200 |
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| 256 | SetExRegByte( DLH1, 0x00 ) # 0x145 is 2400 baud |
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| 257 | SetExRegByte( LCR1, 0x03 ) # enable r/w buffers, IER1 accessible |
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| 258 | # reg 8-n-1 |
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| 259 | SetExRegByte( IER1, 0x00 ) # was 0x0f - All interrupts detected |
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| 260 | |
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[6128a4a] | 261 | SYM(InitMCR): |
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[33442772] | 262 | /* |
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[6128a4a] | 263 | * Initialize Timer for: |
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[33442772] | 264 | * BIT 7 = 1, Timer clocks disabled |
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| 265 | * BIT 6 = 0, Reserved |
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| 266 | * BIT 5 = 1, TMRCLK2 instead of Vcc to Gate2 |
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| 267 | * BIT 4 = 0, PSCLK to CLK2 |
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| 268 | * BIT 3 = 1, TMRCLK1 instead of Vcc to Gate1 |
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| 269 | * BIT 2 = 0, PSCLK to Gate1 |
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[6128a4a] | 270 | * BIT 1 = 0, Vcc to Gate0 |
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[33442772] | 271 | * BIT 0 = 0, PSCLK to Gate0 |
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| 272 | */ |
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| 273 | |
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[6128a4a] | 274 | SYM(InitTimer): |
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| 275 | SetExRegByte(TMRCFG , 0x80 ) # All counters disabled, Gates 0,1 |
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[33442772] | 276 | # and 2 are set to Vcc |
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| 277 | |
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| 278 | SetExRegByte(TMRCON , 0x34 ) # prepare to write counter 0 LSB,MSB |
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[479c86dd] | 279 | SetExRegByte(TMR0 , 0x00 ) # sfa |
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[6128a4a] | 280 | SetExRegByte(TMR0 , 0x00 ) # sfa |
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| 281 | |
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[33442772] | 282 | SetExRegByte(TMRCON , 0x70 ) # mode 0 disables on Gate= Vcc |
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| 283 | SetExRegByte(TMR1 , 0x00 ) # sfa |
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[6128a4a] | 284 | SetExRegByte(TMR1 , 0x00 ) # sfa |
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| 285 | |
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[33442772] | 286 | SetExRegByte(TMRCON , 0xB0 ) # mode 0 disables on gate =Vcc |
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[6128a4a] | 287 | SetExRegByte(TMR2 , 0x00 ) # |
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| 288 | SetExRegByte(TMR2 , 0x00 ) # |
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[479c86dd] | 289 | |
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| 290 | SetExRegByte(TMRCFG , 0x80 ) # Enable = 0x00 |
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[33442772] | 291 | |
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| 292 | /* |
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[6128a4a] | 293 | * Initialize the DMACFG register for: |
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[33442772] | 294 | * BIT 7 = 1 , Disable DACK#1 |
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| 295 | * BITs 6:4 = 100, TMROUT2 connected to DRQ1 |
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| 296 | * BIT 3 = 1 , Disable DACK0# |
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| 297 | * BIT 2:0 = 000, Pin is connected to DRQ0 |
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| 298 | */ |
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| 299 | |
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| 300 | SetExRegByte(DMACFG , 0xC0 ) |
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| 301 | SetExRegByte(DMACMD1, 0x00 ) # disable both DMA channels |
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| 302 | SetExRegByte(DMAMOD1, 0x40 ) |
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| 303 | /* |
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| 304 | * Initialize the INTCFG register for: |
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| 305 | * BIT 7 = 0, 8259 cascade disabled |
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| 306 | * BIT 3 = 0, SLAVE IR6 connected to Vss |
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| 307 | * BIT 2 = 0, SLAVE IR5 connected to Vss |
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| 308 | * BIT 1 = 0, SLAVE IR1 connected to SSIOINT |
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| 309 | * BIT 0 = 0, SLAVE IR0 connected to Vss |
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| 310 | */ |
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| 311 | |
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| 312 | SYM(InitInt): |
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[6128a4a] | 313 | |
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[33442772] | 314 | cli # ! |
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[f70598c7] | 315 | /* SetExRegByte(OCW3S, 0x20) # address the Slave status port |
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[6128a4a] | 316 | movw $OCW3S , dx |
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[f70598c7] | 317 | inb dx , al # Read the IRR. |
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| 318 | |
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[6128a4a] | 319 | SetExRegByte(OCW3M, 0x20) # address the Master status port |
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| 320 | movw $OCW3M , dx |
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[f70598c7] | 321 | inb dx , al # Read the IRR. |
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[6128a4a] | 322 | */ |
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| 323 | |
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[33442772] | 324 | SetExRegByte(ICW1S , 0x11 ) # EDGE TRIGGERED |
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| 325 | SetExRegByte(ICW2S , 0x28 ) # Slave base vector after Master |
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[04bc5d9] | 326 | SetExRegByte(ICW3S , 0x02 ) # slave cascaded to IR2 on master |
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[33442772] | 327 | SetExRegByte(ICW4S , 0x01 ) # must be 0x01 |
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| 328 | |
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| 329 | SetExRegByte(ICW1M , 0x11 ) # edge triggered |
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[04bc5d9] | 330 | SetExRegByte(ICW2M , 0x20 ) # base vector starts at byte 32 |
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| 331 | SetExRegByte(ICW3M , 0x04) # IR2 is cascaded internally |
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[f70598c7] | 332 | SetExRegByte(ICW4M , 0x01 ) # fully nested mode |
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[6128a4a] | 333 | |
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| 334 | SetExRegByte(OCW1M , 0xde ) # IR0 only = 0xfe. |
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[f70598c7] | 335 | # for IR5 and IR0 active use 0xde |
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| 336 | # for IR0 and IR2 use 0xfa |
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[33442772] | 337 | SetExRegByte(INTCFG , 0x00 ) |
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[6128a4a] | 338 | |
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| 339 | SYM(SetCS4): |
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[33442772] | 340 | SetExRegWord(CS4ADL , 0x702) #Configure chip select 4 |
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| 341 | SetExRegWord(CS4ADH , 0x00) |
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[6128a4a] | 342 | SetExRegWord(CS4MSKH, 0x03F) |
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| 343 | SetExRegWord(CS4MSKL, 0xFC01) |
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[33442772] | 344 | |
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[6128a4a] | 345 | SYM(SetUCS1): |
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[33442772] | 346 | SetExRegWord(UCSADL , 0x0304) # 512K block starting at 0x80000 until 0x3f80000 |
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| 347 | SetExRegWord(UCSADH , 0x03F8) |
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[6128a4a] | 348 | SetExRegWord(UCSMSKH, 0x03F7) |
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[33442772] | 349 | SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select |
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| 350 | |
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[04bc5d9] | 351 | /****************************************************** |
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| 352 | * The GDT must be in RAM since it must be writeable, |
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| 353 | * So, move the whole data section down. |
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| 354 | ********************************************************/ |
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[6128a4a] | 355 | |
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[04bc5d9] | 356 | movw $ _ram_data_offset , di |
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[6128a4a] | 357 | movw $ _ram_data_segment, cx |
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[04bc5d9] | 358 | mov cx , es |
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| 359 | |
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[6128a4a] | 360 | movw $ _data_size , cx |
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| 361 | movw $ _rom_data_segment, ax |
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| 362 | movw $ _rom_data_offset , si |
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[04bc5d9] | 363 | mov ax , ds |
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[6128a4a] | 364 | |
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[33442772] | 365 | repne |
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| 366 | movsb |
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[6128a4a] | 367 | |
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[33442772] | 368 | /***************************** |
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| 369 | * Load the Global Descriptor |
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| 370 | * Table Register |
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| 371 | ****************************/ |
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[6128a4a] | 372 | |
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| 373 | #ifdef NEW_GAS |
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[8be7bef] | 374 | data32 addr32 lgdt SYM(GDTR) # location of GDT |
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| 375 | #else |
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[04bc5d9] | 376 | lgdt SYM(GDTR) # location of GDT |
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[6128a4a] | 377 | #endif |
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| 378 | |
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| 379 | SYM(SetUCS): |
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| 380 | SetExRegWord(UCSADL, 0x0702) # now 512K starting at 0x3f80000. |
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[33442772] | 381 | SetExRegWord(UCSADH, 0x03f8) |
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[6128a4a] | 382 | SetExRegWord(UCSMSKH, 0x0007) |
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[33442772] | 383 | SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select |
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[6128a4a] | 384 | |
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[f70598c7] | 385 | /* |
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| 386 | * SRAM chip select: 16 bit bus size,starting 16Mb, size 512k, |
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| 387 | * 4 waits |
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| 388 | */ |
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[6128a4a] | 389 | |
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[f70598c7] | 390 | #ifdef UT_I386EX |
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| 391 | |
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| 392 | SYM(SetCS1): |
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| 393 | SetExRegWord(CS1ADL, 0x0000) |
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| 394 | SetExRegWord(CS1ADH, 0x000E) |
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| 395 | SetExRegWord(CS1MSKH, 0x0000) |
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| 396 | SetExRegWord(CS1MSKL, 0x0001) |
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[33442772] | 397 | |
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[f70598c7] | 398 | SYM(SetCS2): |
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| 399 | SetExRegWord(CS2ADL, 0x0704) |
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| 400 | SetExRegWord(CS2ADH, 0x0100) |
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| 401 | SetExRegWord(CS2MSKH, 0x0003) |
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| 402 | SetExRegWord(CS2MSKL, 0xfc01) |
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| 403 | |
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| 404 | /* |
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| 405 | * Real-time clock: 8 bit bus size, starting@16Mb+512K, size 32k |
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[6128a4a] | 406 | * 4 waits |
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[f70598c7] | 407 | */ |
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| 408 | SYM(SetCS3): |
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| 409 | SetExRegWord(CS3ADL, 0x0504) |
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| 410 | SetExRegWord(CS3ADH, 0x0108) |
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| 411 | SetExRegWord(CS3MSKH, 0x0000) |
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| 412 | SetExRegWord(CS3MSKL, 0x7c01) |
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| 413 | |
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| 414 | #endif |
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[33442772] | 415 | /*************************** |
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| 416 | * Switch to Protected Mode |
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| 417 | ***************************/ |
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[f70598c7] | 418 | |
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[bd8c8b2a] | 419 | mov cr0, eax |
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[33442772] | 420 | orw $0x1, ax |
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[bd8c8b2a] | 421 | mov eax, cr0 |
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[6128a4a] | 422 | |
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[33442772] | 423 | /************************** |
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| 424 | * Flush prefetch queue, |
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| 425 | * and load CS selector |
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| 426 | *********************/ |
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| 427 | |
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[04bc5d9] | 428 | ljmpl $ GDT_CODE_PTR , $ SYM(_load_segment_registers) # sets the code selector |
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[6128a4a] | 429 | |
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[33442772] | 430 | /* |
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[32f3e34] | 431 | * Load the segment registers |
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[33442772] | 432 | */ |
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[6128a4a] | 433 | SYM(_load_segment_registers): |
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[33442772] | 434 | .code32 |
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| 435 | pLOAD_SEGMENT( GDT_DATA_PTR, fs) |
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| 436 | pLOAD_SEGMENT( GDT_DATA_PTR, gs) |
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| 437 | pLOAD_SEGMENT( GDT_DATA_PTR, ss) |
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| 438 | pLOAD_SEGMENT( GDT_DATA_PTR, ds) |
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| 439 | pLOAD_SEGMENT( GDT_DATA_PTR, es) |
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[6128a4a] | 440 | |
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[33442772] | 441 | /* |
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| 442 | * Set up the stack |
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| 443 | */ |
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| 444 | |
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[04bc5d9] | 445 | SYM(lidtr): |
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| 446 | lidt SYM(IDTR) |
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| 447 | |
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[33442772] | 448 | SYM (_establish_stack): |
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| 449 | movl $end, eax # stack starts right after bss |
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| 450 | movl $stack_origin, esp # this is the high starting address |
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| 451 | movl $stack_origin, ebp |
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[f70598c7] | 452 | |
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[33442772] | 453 | /* |
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| 454 | * Zero out the BSS segment |
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| 455 | */ |
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| 456 | SYM (zero_bss): |
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| 457 | cld # make direction flag count up |
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| 458 | movl $ SYM (end),ecx # find end of .bss |
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| 459 | movl $ SYM (_bss_start),edi # edi = beginning of .bss |
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| 460 | subl edi,ecx # ecx = size of .bss in bytes |
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| 461 | shrl ecx # size of .bss in longs |
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| 462 | shrl ecx |
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| 463 | xorl eax,eax # value to clear out memory |
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| 464 | repne # while ecx != 0 |
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| 465 | stosl # clear a long in the bss |
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| 466 | |
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| 467 | /* |
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| 468 | * Transfer control to User's Board Support Package |
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| 469 | */ |
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| 470 | pushl $0 # environp |
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| 471 | pushl $0 # argv |
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| 472 | pushl $0 # argc |
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[f70598c7] | 473 | |
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| 474 | movw $0xFFFB, SYM(i8259s_cache) # ICU mask values reflect |
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[6128a4a] | 475 | # initial ICU state |
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[04bc5d9] | 476 | call SYM(boot_card) |
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[33442772] | 477 | addl $12,esp |
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[32f3e34] | 478 | |
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| 479 | cli # stops interrupts from being processed after hlt! |
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| 480 | hlt # shutdown |
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[33442772] | 481 | |
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| 482 | END |
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