1 | /* |
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2 | * Submitted by: |
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3 | * |
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4 | * Erik Ivanenko |
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5 | * University of Toronto |
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6 | * erik.ivanenko@utoronto.ca |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * http://www.rtems.com/license/LICENSE. |
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11 | * |
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12 | * $Id$ |
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13 | */ |
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14 | |
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15 | /* REMAP ADDRESSING Registers */ |
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16 | .set REMAPCFGH , 0x0023 |
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17 | .set REMAPCFGL , 0x0022 |
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18 | .set REMAPCFG , 0x0022 |
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19 | /* INTERRUPT CONTROL REGISTERS -- SLOT 15 ADDRESSES */ |
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20 | .set ICW1M , 0xF020 |
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21 | .set ICW1S , 0xF0A0 |
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22 | .set ICW2M , 0xF021 |
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23 | .set ICW2S , 0xF0A1 |
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24 | .set ICW3M , 0xF021 |
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25 | .set ICW3S , 0xF0A1 |
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26 | .set ICW4M , 0xF021 |
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27 | .set ICW4S , 0xF0A1 |
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28 | .set OCW1M , 0xF021 |
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29 | .set OCW1S , 0xF0A1 |
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30 | .set OCW2M , 0xF020 |
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31 | .set OCW2S , 0xF0A0 |
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32 | .set OCW3M , 0xF020 |
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33 | .set OCW3S , 0xF0A0 |
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34 | /* INTERRUPT CONTROL REGISTERS -- SLOT 0 ADDRESSES */ |
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35 | .set ICW1MDOS , 0x0020 |
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36 | .set ICW1SDOS , 0x00A0 |
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37 | .set ICW2MDOS , 0x0021 |
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38 | .set ICW2SDOS , 0x00A1 |
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39 | .set ICW3MDOS , 0x0021 |
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40 | .set ICW3SDOS , 0x00A1 |
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41 | .set ICW4MDOS , 0x0021 |
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42 | .set ICW4SDOS , 0x00A1 |
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43 | .set OCW1MDOS , 0x0021 |
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44 | .set OCW1SDOS , 0x00A1 |
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45 | .set OCW2MDOS , 0x0020 |
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46 | .set OCW2SDOS , 0x00A0 |
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47 | .set OCW3MDOS , 0x0020 |
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48 | .set OCW3SDOS , 0x00A0 |
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49 | |
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50 | |
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51 | /* CONFIGURATION Registers */ |
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52 | .set DMACFG , 0xF830 |
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53 | .set INTCFG , 0xF832 |
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54 | .set TMRCFG , 0xF834 |
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55 | .set SIOCFG , 0xF836 |
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56 | .set P1CFG , 0xF820 |
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57 | .set P2CFG , 0xF822 |
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58 | .set P3CFG , 0xF824 |
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59 | .set PINCFG , 0xF826 |
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60 | |
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61 | /* WATCHDOG TIMER Registers */ |
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62 | .set WDTRLDH , 0xF4C0 |
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63 | .set WDTRLDL , 0xF4C2 |
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64 | .set WDTCNTH , 0xF4C4 |
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65 | .set WDTCNTL , 0xF4C6 |
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66 | .set WDTCLR , 0xF4C8 |
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67 | .set WDTSTATUS , 0xF4CA |
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68 | |
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69 | /* TIMER CONTROL REGISTERS -- SLOT 15 ADDRESSES */ |
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70 | .set TMR0 , 0xF040 |
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71 | .set TMR1 , 0xF041 |
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72 | .set TMR2 , 0xF042 |
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73 | .set TMRCON , 0xF043 |
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74 | /* TIMER CONTROL REGISTERS -- SLOT 0 ADDRESSES */ |
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75 | .set TMR0DOS , 0x0040 |
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76 | .set TMR1DOS , 0x0041 |
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77 | .set TMR2DOS , 0x0042 |
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78 | .set TMRCONDOS , 0x0043 |
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79 | |
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80 | /* INPUT/OUTPUT PORT UNIT Registers */ |
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81 | .set P1PIN , 0xF860 |
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82 | .set P1LTC , 0xF862 |
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83 | .set P1DIR , 0xF864 |
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84 | .set P2PIN , 0xF868 |
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85 | .set P2LTC , 0xF86A |
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86 | .set P2DIR , 0xF86C |
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87 | .set P3PIN , 0xF870 |
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88 | .set P3LTC , 0xF872 |
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89 | .set P3DIR , 0xF874 |
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90 | |
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91 | /* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 15 ADDRESSES */ |
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92 | .set RBR0 , 0xF4F8 |
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93 | .set THR0 , 0xF4F8 |
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94 | .set TBR0 , 0xF4F8 |
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95 | .set DLL0 , 0xF4F8 |
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96 | .set IER0 , 0xF4F9 |
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97 | .set DLH0 , 0xF4F9 |
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98 | .set IIR0 , 0xF4FA |
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99 | .set LCR0 , 0xF4FB |
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100 | .set MCR0 , 0xF4FC |
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101 | .set LSR0 , 0xF4FD |
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102 | .set MSR0 , 0xF4FE |
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103 | .set SCR0 , 0xF4FF |
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104 | /* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 0 ADDRESSES */ |
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105 | .set RBR0DOS , 0x03F8 |
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106 | .set THR0DOS , 0x03F8 |
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107 | .set TBR0DOS , 0x03F8 |
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108 | .set DLL0DOS , 0x03F8 |
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109 | .set IER0DOS , 0x03F9 |
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110 | .set DLH0DOS , 0x03F9 |
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111 | .set IIR0DOS , 0x03FA |
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112 | .set LCR0DOS , 0x03FB |
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113 | .set MCR0DOS , 0x03FC |
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114 | .set LSR0DOS , 0x03FD |
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115 | .set MSR0DOS , 0x03FE |
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116 | .set SCR0DOS , 0x03FF |
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117 | |
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118 | /* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 15 ADDRESSES */ |
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119 | .set RBR1 , 0xF8F8 |
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120 | .set THR1 , 0xF8F8 |
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121 | .set TBR1 , 0XF8F8 |
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122 | .set DLL1 , 0xF8F8 |
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123 | .set IER1 , 0xF8F9 |
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124 | .set DLH1 , 0xF8F9 |
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125 | .set IIR1 , 0xF8FA |
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126 | .set LCR1 , 0xF8FB |
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127 | .set MCR1 , 0xF8FC |
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128 | .set LSR1 , 0xF8FD |
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129 | .set MSR1 , 0xF8FE |
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130 | .set SCR1 , 0xF8FF |
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131 | /* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 0 ADDRESSES */ |
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132 | .set RBR1DOS , 0x02F8 |
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133 | .set THR1DOS , 0x02F8 |
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134 | .set TBR1DOS , 0x02F8 |
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135 | .set DLL1DOS , 0x02F8 |
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136 | .set IER1DOS , 0x02F9 |
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137 | .set DLH1DOS , 0x02F9 |
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138 | .set IIR1DOS , 0x02FA |
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139 | .set LCR1DOS , 0x02FB |
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140 | .set MCR1DOS , 0x02FC |
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141 | .set LSR1DOS , 0x02FD |
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142 | .set MSR1DOS , 0x02FE |
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143 | .set SCR1DOS , 0x02FF |
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144 | |
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145 | /* SYNCHRONOUS SERIAL CHANNEL REGISTERS */ |
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146 | .set SSIOTBUF , 0xF480 |
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147 | .set SSIORBUF , 0xF482 |
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148 | .set SSIOBAUD , 0xF484 |
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149 | .set SSIOCON1 , 0xF486 |
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150 | .set SSIOCON2 , 0xF488 |
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151 | .set SSIOCTR , 0xF48A |
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152 | |
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153 | /* CHIP SELECT UNIT Registers */ |
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154 | .set CS0ADL , 0xF400 |
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155 | .set CS0ADH , 0xF402 |
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156 | .set CS0MSKL , 0xF404 |
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157 | .set CS0MSKH , 0xF406 |
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158 | .set CS1ADL , 0xF408 |
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159 | .set CS1ADH , 0xF40A |
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160 | .set CS1MSKL , 0xF40C |
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161 | .set CS1MSKH , 0xF40E |
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162 | .set CS2ADL , 0xF410 |
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163 | .set CS2ADH , 0xF412 |
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164 | .set CS2MSKL , 0xF414 |
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165 | .set CS2MSKH , 0xF416 |
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166 | .set CS3ADL , 0xF418 |
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167 | .set CS3ADH , 0xF41A |
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168 | .set CS3MSKL , 0xF41C |
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169 | .set CS3MSKH , 0xF41E |
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170 | .set CS4ADL , 0xF420 |
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171 | .set CS4ADH , 0xF422 |
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172 | .set CS4MSKL , 0xF424 |
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173 | .set CS4MSKH , 0xF426 |
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174 | .set CS5ADL , 0xF428 |
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175 | .set CS5ADH , 0xF42A |
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176 | .set CS5MSKL , 0xF42C |
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177 | .set CS5MSKH , 0xF42E |
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178 | .set CS6ADL , 0xF430 |
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179 | .set CS6ADH , 0xF432 |
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180 | .set CS6MSKL , 0xF434 |
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181 | .set CS6MSKH , 0xF436 |
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182 | .set UCSADL , 0xF438 |
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183 | .set UCSADH , 0xF43A |
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184 | .set UCSMSKL , 0xF43C |
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185 | .set UCSMSKH , 0xF43E |
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186 | |
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187 | /* REFRESH CONTROL UNIT Registers */ |
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188 | |
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189 | .set RFSBAD , 0xF4A0 |
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190 | .set RFSCIR , 0xF4A2 |
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191 | .set RFSCON , 0xF4A4 |
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192 | .set RFSADD , 0xF4A6 |
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193 | |
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194 | /* POWER MANAGEMENT CONTROL Registers */ |
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195 | |
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196 | .set PWRCON , 0xF800 |
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197 | .set CLKPRS , 0xF804 |
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198 | |
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199 | /* DMA UNIT REGISTERS -- SLOT 15 ADDRESSES */ |
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200 | .set DMA0TAR , 0xF000 |
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201 | .set DMA0BYC , 0xF001 |
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202 | .set DMA1TAR , 0xF002 |
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203 | .set DMA1BYC , 0xF003 |
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204 | .set DMACMD1 , 0xF008 |
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205 | .set DMASTS , 0xF008 |
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206 | .set DMASRR , 0xF009 |
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207 | .set DMAMSK , 0xF00A |
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208 | .set DMAMOD1 , 0xF00B |
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209 | .set DMACLRBP , 0xF00C |
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210 | .set DMACLR , 0xF00D |
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211 | .set DMACLRMSK , 0xF00E |
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212 | .set DMAGRPMSK , 0xF00F |
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213 | .set DMA0REQL , 0xF010 |
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214 | .set DMA0REQH , 0xF011 |
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215 | .set DMA1REQL , 0xF012 |
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216 | .set DMA1REQH , 0xF013 |
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217 | .set DMABSR , 0xF018 |
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218 | .set DMACHR , 0xF019 |
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219 | .set DMAIS , 0xF019 |
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220 | .set DMACMD2 , 0xF01A |
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221 | .set DMAMOD2 , 0xF01B |
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222 | .set DMAIEN , 0xF01C |
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223 | .set DMAOVFE , 0xF01D |
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224 | .set DMACLRTC , 0xF01E |
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225 | .set DMA1TARPL , 0xF083 |
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226 | .set DMA1TARPH , 0xF085 |
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227 | .set DMA0TARPH , 0xF086 |
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228 | .set DMA0TARPL , 0xF087 |
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229 | .set DMA0BYCH , 0xF098 |
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230 | .set DMA1BYCH , 0xF099 |
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231 | |
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232 | /* DMA UNIT REGISTERS -- SLOT 0 ADDRESSES */ |
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233 | .set DMA0TARDOS , 0x0000 |
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234 | .set DMA0BYCDOS , 0x0001 |
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235 | .set DMA1TARDOS , 0x0002 |
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236 | .set DMA1BYCDOS , 0x0003 |
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237 | .set DMACMD1DOS , 0x0008 |
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238 | .set DMASTSDOS , 0x0008 |
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239 | .set DMASRRDOS , 0x0009 |
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240 | .set DMAMSKDOS , 0x000A |
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241 | .set DMAMOD1DOS , 0x000B |
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242 | .set DMACLRBPDOS , 0x000C |
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243 | .set DMACLRDOS , 0x000D |
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244 | .set DMACLRMSKDOS , 0x000E |
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245 | .set DMAGRPMSKDOS , 0x000F |
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246 | .set DMA1TARPLDOS , 0x0083 |
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247 | .set DMA0TARPLDOS , 0x0087 |
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248 | |
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249 | /* A20GATE AND FAST CPU RESET -- SLOT 15 ADDRESS */ |
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250 | .set PORT92 , 0xF092 |
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251 | /* A20GATE AND FAST CPU RESET -- SLOT 0 ADDRESS */ |
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252 | .set PORT92DOS , 0x0092 |
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