1 | /* |
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2 | * Submitted by: |
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3 | * |
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4 | * Erik Ivanenko |
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5 | * University of Toronto |
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6 | * erik.ivanenko@utoronto.ca |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * http://www.rtems.com/license/LICENSE. |
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11 | * |
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12 | * $Id$ |
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13 | */ |
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14 | |
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15 | /* REMAP ADDRESSING Registers */ |
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16 | #define REMAPCFGH 0x0023 |
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17 | #define REMAPCFGL 0x0022 |
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18 | #define REMAPCFG 0x0022 |
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19 | /* INTERRUPT CONTROL REGISTERS -- SLOT 15 ADDRESSES */ |
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20 | #define ICW1M 0xF020 |
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21 | #define ICW1S 0xF0A0 |
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22 | #define ICW2M 0xF021 |
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23 | #define ICW2S 0xF0A1 |
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24 | #define ICW3M 0xF021 |
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25 | #define ICW3S 0xF0A1 |
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26 | #define ICW4M 0xF021 |
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27 | #define ICW4S 0xF0A1 |
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28 | #define OCW1M 0xF021 |
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29 | #define OCW1S 0xF0A1 |
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30 | #define OCW2M 0xF020 |
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31 | #define OCW2S 0xF0A0 |
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32 | #define OCW3M 0xF020 |
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33 | #define OCW3S 0xF0A0 |
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34 | /* INTERRUPT CONTROL REGISTERS -- SLOT 0 ADDRESSES */ |
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35 | #define ICW1MDOS 0x0020 |
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36 | #define ICW1SDOS 0x00A0 |
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37 | #define ICW2MDOS 0x0021 |
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38 | #define ICW2SDOS 0x00A1 |
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39 | #define ICW3MDOS 0x0021 |
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40 | #define ICW3SDOS 0x00A1 |
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41 | #define ICW4MDOS 0x0021 |
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42 | #define ICW4SDOS 0x00A1 |
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43 | #define OCW1MDOS 0x0021 |
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44 | #define OCW1SDOS 0x00A1 |
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45 | #define OCW2MDOS 0x0020 |
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46 | #define OCW2SDOS 0x00A0 |
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47 | #define OCW3MDOS 0x0020 |
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48 | #define OCW3SDOS 0x00A0 |
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49 | |
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50 | |
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51 | /* CONFIGURATION Registers */ |
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52 | #define DMACFG 0xF830 |
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53 | #define INTCFG 0xF832 |
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54 | #define TMRCFG 0xF834 |
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55 | #define SIOCFG 0xF836 |
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56 | #define P1CFG 0xF820 |
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57 | #define P2CFG 0xF822 |
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58 | #define P3CFG 0xF824 |
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59 | #define PINCFG 0xF826 |
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60 | |
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61 | /* WATCHDOG TIMER Registers */ |
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62 | #define WDTRLDH 0xF4C0 |
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63 | #define WDTRLDL 0xF4C2 |
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64 | #define WDTCNTH 0xF4C4 |
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65 | #define WDTCNTL 0xF4C6 |
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66 | #define WDTCLR 0xF4C8 |
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67 | #define WDTSTATUS 0xF4CA |
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68 | |
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69 | /* TIMER CONTROL REGISTERS -- SLOT 15 ADDRESSES */ |
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70 | #define TMR0 0xF040 |
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71 | #define TMR1 0xF041 |
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72 | #define TMR2 0xF042 |
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73 | #define TMRCON 0xF043 |
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74 | /* TIMER CONTROL REGISTERS -- SLOT 0 ADDRESSES */ |
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75 | #define TMR0DOS 0x0040 |
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76 | #define TMR1DOS 0x0041 |
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77 | #define TMR2DOS 0x0042 |
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78 | #define TMRCONDOS 0x0043 |
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79 | |
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80 | /* INPUT/OUTPUT PORT UNIT Registers */ |
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81 | #define P1PIN 0xF860 |
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82 | #define P1LTC 0xF862 |
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83 | #define P1DIR 0xF864 |
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84 | #define P2PIN 0xF868 |
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85 | #define P2LTC 0xF86A |
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86 | #define P2DIR 0xF86C |
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87 | #define P3PIN 0xF870 |
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88 | #define P3LTC 0xF872 |
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89 | #define P3DIR 0xF874 |
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90 | |
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91 | /* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 15 ADDRESSES */ |
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92 | #define RBR0 0xF4F8 |
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93 | #define THR0 0xF4F8 |
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94 | #define TBR0 0xF4F8 |
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95 | #define DLL0 0xF4F8 |
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96 | #define IER0 0xF4F9 |
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97 | #define DLH0 0xF4F9 |
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98 | #define IIR0 0xF4FA |
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99 | #define LCR0 0xF4FB |
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100 | #define MCR0 0xF4FC |
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101 | #define LSR0 0xF4FD |
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102 | #define MSR0 0xF4FE |
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103 | #define SCR0 0xF4FF |
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104 | /* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 0 ADDRESSES */ |
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105 | #define RBR0DOS 0x03F8 |
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106 | #define THR0DOS 0x03F8 |
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107 | #define TBR0DOS 0x03F8 |
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108 | #define DLL0DOS 0x03F8 |
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109 | #define IER0DOS 0x03F9 |
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110 | #define DLH0DOS 0x03F9 |
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111 | #define IIR0DOS 0x03FA |
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112 | #define LCR0DOS 0x03FB |
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113 | #define MCR0DOS 0x03FC |
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114 | #define LSR0DOS 0x03FD |
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115 | #define MSR0DOS 0x03FE |
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116 | #define SCR0DOS 0x03FF |
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117 | |
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118 | /* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 15 ADDRESSES */ |
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119 | #define RBR1 0xF8F8 |
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120 | #define THR1 0xF8F8 |
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121 | #define TBR1 0XF8F8 |
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122 | #define DLL1 0xF8F8 |
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123 | #define IER1 0xF8F9 |
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124 | #define DLH1 0xF8F9 |
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125 | #define IIR1 0xF8FA |
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126 | #define LCR1 0xF8FB |
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127 | #define MCR1 0xF8FC |
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128 | #define LSR1 0xF8FD |
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129 | #define MSR1 0xF8FE |
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130 | #define SCR1 0xF8FF |
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131 | /* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 0 ADDRESSES */ |
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132 | #define RBR1DOS 0x02F8 |
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133 | #define THR1DOS 0x02F8 |
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134 | #define TBR1DOS 0x02F8 |
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135 | #define DLL1DOS 0x02F8 |
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136 | #define IER1DOS 0x02F9 |
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137 | #define DLH1DOS 0x02F9 |
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138 | #define IIR1DOS 0x02FA |
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139 | #define LCR1DOS 0x02FB |
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140 | #define MCR1DOS 0x02FC |
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141 | #define LSR1DOS 0x02FD |
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142 | #define MSR1DOS 0x02FE |
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143 | #define SCR1DOS 0x02FF |
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144 | |
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145 | /* SYNCHRONOUS SERIAL CHANNEL REGISTERS */ |
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146 | #define SSIOTBUF 0xF480 |
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147 | #define SSIORBUF 0xF482 |
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148 | #define SSIOBAUD 0xF484 |
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149 | #define SSIOCON1 0xF486 |
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150 | #define SSIOCON2 0xF488 |
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151 | #define SSIOCTR 0xF48A |
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152 | |
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153 | /* CHIP SELECT UNIT Registers */ |
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154 | #define CS0ADL 0xF400 |
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155 | #define CS0ADH 0xF402 |
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156 | #define CS0MSKL 0xF404 |
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157 | #define CS0MSKH 0xF406 |
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158 | #define CS1ADL 0xF408 |
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159 | #define CS1ADH 0xF40A |
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160 | #define CS1MSKL 0xF40C |
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161 | #define CS1MSKH 0xF40E |
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162 | #define CS2ADL 0xF410 |
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163 | #define CS2ADH 0xF412 |
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164 | #define CS2MSKL 0xF414 |
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165 | #define CS2MSKH 0xF416 |
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166 | #define CS3ADL 0xF418 |
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167 | #define CS3ADH 0xF41A |
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168 | #define CS3MSKL 0xF41C |
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169 | #define CS3MSKH 0xF41E |
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170 | #define CS4ADL 0xF420 |
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171 | #define CS4ADH 0xF422 |
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172 | #define CS4MSKL 0xF424 |
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173 | #define CS4MSKH 0xF426 |
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174 | #define CS5ADL 0xF428 |
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175 | #define CS5ADH 0xF42A |
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176 | #define CS5MSKL 0xF42C |
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177 | #define CS5MSKH 0xF42E |
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178 | #define CS6ADL 0xF430 |
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179 | #define CS6ADH 0xF432 |
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180 | #define CS6MSKL 0xF434 |
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181 | #define CS6MSKH 0xF436 |
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182 | #define UCSADL 0xF438 |
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183 | #define UCSADH 0xF43A |
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184 | #define UCSMSKL 0xF43C |
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185 | #define UCSMSKH 0xF43E |
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186 | |
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187 | /* REFRESH CONTROL UNIT Registers */ |
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188 | |
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189 | #define RFSBAD 0xF4A0 |
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190 | #define RFSCIR 0xF4A2 |
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191 | #define RFSCON 0xF4A4 |
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192 | #define RFSADD 0xF4A6 |
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193 | |
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194 | /* POWER MANAGEMENT CONTROL Registers */ |
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195 | |
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196 | #define PWRCON 0xF800 |
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197 | #define CLKPRS 0xF804 |
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198 | |
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199 | /* DMA UNIT REGISTERS -- SLOT 15 ADDRESSES */ |
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200 | #define DMA0TAR 0xF000 |
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201 | #define DMA0BYC 0xF001 |
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202 | #define DMA1TAR 0xF002 |
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203 | #define DMA1BYC 0xF003 |
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204 | #define DMACMD1 0xF008 |
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205 | #define DMASTS 0xF008 |
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206 | #define DMASRR 0xF009 |
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207 | #define DMAMSK 0xF00A |
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208 | #define DMAMOD1 0xF00B |
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209 | #define DMACLRBP 0xF00C |
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210 | #define DMACLR 0xF00D |
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211 | #define DMACLRMSK 0xF00E |
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212 | #define DMAGRPMSK 0xF00F |
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213 | #define DMA0REQL 0xF010 |
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214 | #define DMA0REQH 0xF011 |
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215 | #define DMA1REQL 0xF012 |
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216 | #define DMA1REQH 0xF013 |
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217 | #define DMABSR 0xF018 |
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218 | #define DMACHR 0xF019 |
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219 | #define DMAIS 0xF019 |
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220 | #define DMACMD2 0xF01A |
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221 | #define DMAMOD2 0xF01B |
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222 | #define DMAIEN 0xF01C |
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223 | #define DMAOVFE 0xF01D |
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224 | #define DMACLRTC 0xF01E |
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225 | #define DMA1TARPL 0xF083 |
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226 | #define DMA1TARPH 0xF085 |
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227 | #define DMA0TARPH 0xF086 |
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228 | #define DMA0TARPL 0xF087 |
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229 | #define DMA0BYCH 0xF098 |
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230 | #define DMA1BYCH 0xF099 |
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231 | |
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232 | /* DMA UNIT REGISTERS -- SLOT 0 ADDRESSES */ |
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233 | #define DMA0TARDOS 0x0000 |
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234 | #define DMA0BYCDOS 0x0001 |
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235 | #define DMA1TARDOS 0x0002 |
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236 | #define DMA1BYCDOS 0x0003 |
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237 | #define DMACMD1DOS 0x0008 |
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238 | #define DMASTSDOS 0x0008 |
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239 | #define DMASRRDOS 0x0009 |
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240 | #define DMAMSKDOS 0x000A |
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241 | #define DMAMOD1DOS 0x000B |
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242 | #define DMACLRBPDOS 0x000C |
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243 | #define DMACLRDOS 0x000D |
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244 | #define DMACLRMSKDOS 0x000E |
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245 | #define DMAGRPMSKDOS 0x000F |
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246 | #define DMA1TARPLDOS 0x0083 |
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247 | #define DMA0TARPLDOS 0x0087 |
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248 | |
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249 | /* A20GATE AND FAST CPU RESET -- SLOT 15 ADDRESS */ |
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250 | #define PORT92 0xF092 |
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251 | /* A20GATE AND FAST CPU RESET -- SLOT 0 ADDRESS */ |
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252 | #define PORT92DOS 0x0092 |
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253 | |
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254 | /* end of include file */ |
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