1 | |
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2 | /* uti596.h: Contains the defines and structures used by the uti596 driver */ |
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3 | |
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4 | /* |
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5 | * EII: March 11: Created v. 0.0 |
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6 | * Jan 12/98 Added STAT bits, s11-=s5 and max_colls. |
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7 | * |
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8 | * $Id$ |
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9 | */ |
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10 | |
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11 | #ifndef UTI596_H |
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12 | #define UTI596_H |
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13 | #include <rtems/error.h> |
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14 | #include <rtems/rtems_bsdnet.h> |
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15 | |
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16 | #include <sys/param.h> |
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17 | #include <sys/mbuf.h> |
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18 | #include <sys/socket.h> |
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19 | #include <sys/sockio.h> |
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20 | |
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21 | #include <net/if.h> |
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22 | |
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23 | #include <netinet/in.h> |
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24 | #include <netinet/if_ether.h> |
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25 | |
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26 | /* Ethernet statistics */ |
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27 | |
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28 | struct enet_statistics{ |
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29 | int rx_packets; /* total packets received */ |
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30 | int tx_packets; /* total packets transmitted */ |
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31 | int rx_errors; /* bad packets received */ |
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32 | int tx_errors; /* packet transmit problems */ |
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33 | int rx_dropped; /* no space in buffers */ |
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34 | int tx_dropped; /* */ |
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35 | int tx_retries_exceeded; /* excessive retries */ |
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36 | int multicast; /* multicast packets received */ |
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37 | int collisions; |
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38 | |
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39 | /* detailed rx_errors: */ |
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40 | int rx_length_errors; |
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41 | int rx_over_errors; /* receiver ring buff overflow */ |
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42 | int rx_crc_errors; /* recved pkt with crc error */ |
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43 | int rx_frame_errors; /* recv'd frame alignment error */ |
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44 | int rx_fifo_errors; /* recv'r fifo overrun */ |
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45 | int rx_missed_errors; /* receiver missed packet */ |
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46 | |
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47 | /* detailed tx_errors */ |
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48 | int tx_aborted_errors; |
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49 | int tx_carrier_errors; |
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50 | int tx_fifo_errors; |
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51 | int tx_heartbeat_errors; |
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52 | int tx_window_errors; |
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53 | |
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54 | /* NIC reset errors */ |
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55 | int nic_reset_count; /* The number of times uti596reset() has been called. */ |
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56 | }; |
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57 | |
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58 | |
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59 | |
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60 | enum commands { |
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61 | CmdNOp = 0, |
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62 | CmdSASetup = 1, |
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63 | CmdConfigure = 2, |
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64 | CmdMulticastList = 3, |
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65 | CmdTx = 4, |
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66 | CmdTDR = 5, |
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67 | CmdDump = 6, |
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68 | CmdDiagnose = 7 |
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69 | }; |
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70 | |
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71 | |
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72 | #define UTI596_MUTEX 1 |
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73 | |
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74 | |
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75 | #define CMD_EOL 0x8000 /* The last command of the list, stop. */ |
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76 | #define CMD_SUSP 0x4000 /* Suspend after doing cmd. */ |
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77 | #define CMD_INTR 0x2000 /* Interrupt after doing cmd. */ |
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78 | |
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79 | #define CMD_FLEX 0x0008 /* Enable flexible memory model */ |
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80 | |
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81 | #define SCB_STAT_CX 0x8000 /* Cmd completes with 'I' bit set */ |
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82 | #define SCB_STAT_FR 0x4000 /* Frame Received */ |
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83 | #define SCB_STAT_CNA 0x2000 /* Cmd unit Not Active */ |
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84 | #define SCB_STAT_RNR 0x1000 /* Receiver Not Ready */ |
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85 | |
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86 | #define SCB_CUS_SUSPENDED 0x0100 |
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87 | #define SCB_CUS_ACTIVE 0x0200 |
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88 | |
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89 | |
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90 | #define STAT_C 0x8000 /* Set to 1 after execution */ |
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91 | #define STAT_B 0x4000 /* 1 : Cmd being executed, 0 : Cmd done. */ |
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92 | #define STAT_OK 0x2000 /* 1: Command executed ok 0 : Error */ |
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93 | #define STAT_A 0x1000 /* command has been aborted */ |
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94 | |
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95 | #define STAT_S11 0x0800 |
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96 | #define STAT_S10 0x0400 |
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97 | #define STAT_S9 0x0200 |
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98 | #define STAT_S8 0x0100 |
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99 | #define STAT_S7 0x0080 |
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100 | #define STAT_S6 0x0040 |
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101 | #define STAT_S5 0x0020 |
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102 | #define STAT_MAX_COLLS 0x000F |
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103 | |
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104 | |
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105 | #define RBD_STAT_P 0x4000 /* prefetch */ |
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106 | #define RBD_STAT_F 0x4000 /* used */ |
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107 | |
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108 | #define CUC_START 0x0100 |
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109 | #define CUC_RESUME 0x0200 |
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110 | #define CUC_SUSPEND 0x0300 |
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111 | #define CUC_ABORT 0x0400 |
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112 | #define RX_START 0x0010 |
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113 | #define RX_RESUME 0x0020 |
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114 | #define RX_SUSPEND 0x0030 |
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115 | #define RX_ABORT 0x0040 |
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116 | |
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117 | #define RU_SUSPENDED 0x0010 |
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118 | #define RU_NO_RESOURCES 0x0020 |
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119 | #define RU_READY 0x0040 |
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120 | |
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121 | |
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122 | #define IO_ADDR 0x360 |
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123 | #define PORT_ADDR IO_ADDR |
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124 | #define CHAN_ATTN PORT_ADDR + 4 |
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125 | #define NIC_ADDR PORT_ADDR + 8 |
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126 | |
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127 | struct i596_cmd { |
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128 | volatile unsigned short status; |
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129 | volatile unsigned short command; |
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130 | struct i596_cmd *next; |
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131 | }; |
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132 | |
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133 | #define I596_NULL ( ( void * ) 0xffffffff) |
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134 | #define UTI_596_END_OF_FRAME 0x8000 |
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135 | #define SIZE_MASK 0x3fff |
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136 | |
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137 | /* |
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138 | * Transmit buffer Descriptor |
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139 | */ |
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140 | |
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141 | struct i596_tbd { |
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142 | unsigned short size; |
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143 | unsigned short pad; |
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144 | struct i596_tbd *next; |
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145 | char *data; |
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146 | }; |
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147 | |
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148 | /* |
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149 | * Receive buffer Descriptor |
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150 | */ |
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151 | |
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152 | struct i596_rbd { |
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153 | unsigned short count; |
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154 | unsigned short offset; |
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155 | struct i596_rbd *next; |
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156 | char *data; |
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157 | unsigned short size; |
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158 | unsigned short pad; |
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159 | }; |
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160 | |
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161 | /* |
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162 | * Transmit Command Structure |
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163 | */ |
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164 | struct tx_cmd { |
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165 | struct i596_cmd cmd; |
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166 | struct i596_tbd *pTbd; |
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167 | unsigned short size; |
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168 | unsigned short pad; |
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169 | } ; |
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170 | |
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171 | |
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172 | /* |
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173 | * Receive Frame Descriptor |
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174 | */ |
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175 | struct i596_rfd { |
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176 | volatile unsigned short stat; |
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177 | volatile unsigned short cmd; |
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178 | struct i596_rfd *next; |
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179 | struct i596_rbd *pRbd; |
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180 | unsigned short count; |
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181 | unsigned short size; |
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182 | char data [1532 ]; |
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183 | } ; |
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184 | |
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185 | |
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186 | struct i596_dump { |
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187 | struct i596_cmd cmd; |
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188 | char * pData; |
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189 | }; |
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190 | |
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191 | struct i596_set_add { |
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192 | struct i596_cmd cmd; |
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193 | char data[8]; |
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194 | }; |
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195 | |
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196 | struct i596_configure { |
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197 | struct i596_cmd cmd; |
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198 | char data[16]; |
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199 | }; |
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200 | |
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201 | struct i596_nop { |
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202 | struct i596_cmd cmd; |
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203 | }; |
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204 | |
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205 | struct i596_tdr { |
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206 | struct i596_cmd cmd; |
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207 | unsigned int data; |
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208 | }; |
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209 | |
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210 | #define RX_RING_SIZE 8 |
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211 | |
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212 | /* |
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213 | * System Control Block |
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214 | */ |
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215 | struct i596_scb { |
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216 | volatile unsigned short status; |
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217 | volatile unsigned short command; |
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218 | struct i596_cmd *pCmd; |
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219 | struct i596_rfd *pRfd; |
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220 | volatile unsigned long crc_err; |
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221 | volatile unsigned long align_err; |
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222 | volatile unsigned long resource_err; |
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223 | volatile unsigned long over_err; |
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224 | volatile unsigned long rcvdt_err; |
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225 | volatile unsigned long short_err; |
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226 | volatile unsigned short t_on; |
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227 | volatile unsigned short t_off; |
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228 | }; |
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229 | |
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230 | |
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231 | /* |
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232 | * Intermediate System Control Block |
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233 | */ |
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234 | struct i596_iscp { |
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235 | volatile unsigned long stat; |
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236 | struct i596_scb *scb; |
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237 | } ; |
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238 | /* |
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239 | * System Control Parameters |
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240 | */ |
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241 | struct i596_scp { |
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242 | unsigned long sysbus; |
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243 | unsigned long pad; |
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244 | struct i596_iscp *iscp; |
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245 | } ; |
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246 | |
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247 | struct uti596_softc { |
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248 | struct arpcom arpcom; |
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249 | rtems_irq_connect_data irqInfo; |
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250 | struct i596_scp *pScp; |
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251 | struct i596_iscp iscp; |
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252 | struct i596_scb scb; |
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253 | struct i596_set_add set_add; |
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254 | struct i596_configure set_conf; |
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255 | struct i596_tdr tdr; |
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256 | struct i596_nop nop; |
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257 | unsigned long stat; |
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258 | struct tx_cmd *pTxCmd; |
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259 | struct i596_tbd *pTbd; |
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260 | |
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261 | int ioAddr; |
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262 | |
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263 | struct i596_rfd *pBeginRFA; |
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264 | struct i596_rfd *pEndRFA; |
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265 | struct i596_rfd *pLastUnkRFD; |
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266 | struct i596_rbd *pLastUnkRBD; |
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267 | struct i596_rfd *pEndSavedQueue; |
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268 | struct i596_cmd *pCmdHead; |
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269 | struct i596_cmd *pCmdTail; /* unneeded, as chaining not used, but implemented */ |
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270 | |
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271 | rtems_id rxDaemonTid; |
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272 | rtems_id txDaemonTid; |
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273 | rtems_id resetDaemonTid; |
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274 | |
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275 | struct enet_statistics stats; |
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276 | int started; |
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277 | unsigned long rxInterrupts; |
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278 | unsigned long txInterrupts; |
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279 | volatile int cmdOk; |
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280 | int resetDone; |
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281 | unsigned long txRawWait; |
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282 | struct i596_rfd *pInboundFrameQueue; |
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283 | short int rxBdCount; |
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284 | short int txBdCount; |
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285 | short int countRFD; |
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286 | short int savedCount; |
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287 | struct i596_rfd *pSavedRfdQueue; |
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288 | rtems_name semaphore_name; |
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289 | rtems_id semaphore_id; |
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290 | char zeroes[64]; |
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291 | unsigned long rawsndcnt; |
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292 | int nic_reset; /* flag is for requesting that ISR issue a reset quest */ |
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293 | } ; |
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294 | #endif |
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