source: rtems/c/src/lib/libbsp/i386/i386ex/network/dma.h @ 20ad9e9d

4.104.114.84.95
Last change on this file since 20ad9e9d was 20ad9e9d, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 23, 1998 at 2:28:09 PM

New network driver from Erik Ivanenko <erik.ivanenko@…>.

  • Property mode set to 100644
File size: 8.8 KB
Line 
1/* $Id$
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 */
7
8#ifndef _ASM_DMA_H
9#define _ASM_DMA_H
10
11
12
13#define dma_outb(x,y)   outport_byte(y,x)
14
15#define dma_inb         inport_byte
16
17/*
18 * NOTES about DMA transfers:
19 *
20 *  controller 1: channels 0-3, byte operations, ports 00-1F
21 *  controller 2: channels 4-7, word operations, ports C0-DF
22 *
23 *  - ALL registers are 8 bits only, regardless of transfer size
24 *  - channel 4 is not used - cascades 1 into 2.
25 *  - channels 0-3 are byte - addresses/counts are for physical bytes
26 *  - channels 5-7 are word - addresses/counts are for physical words
27 *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
28 *  - transfer count loaded to registers is 1 less than actual count
29 *  - controller 2 offsets are all even (2x offsets for controller 1)
30 *  - page registers for 5-7 don't use data bit 0, represent 128K pages
31 *  - page registers for 0-3 use bit 0, represent 64K pages
32 *
33 * DMA transfers are limited to the lower 16MB of _physical_ memory. 
34 * Note that addresses loaded into registers must be _physical_ addresses,
35 * not logical addresses (which may differ if paging is active).
36 *
37 *  Address mapping for channels 0-3:
38 *
39 *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
40 *    |  ...  |   |  ... |   |  ... |
41 *    |  ...  |   |  ... |   |  ... |
42 *    |  ...  |   |  ... |   |  ... |
43 *   P7  ...  P0  A7 ... A0  A7 ... A0   
44 * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
45 *
46 *  Address mapping for channels 5-7:
47 *
48 *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
49 *    |  ...  |   \   \   ... \  \  \  ... \  \
50 *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
51 *    |  ...  |     \   \   ... \  \  \  ... \
52 *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0   
53 * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
54 *
55 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
56 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
57 * the hardware level, so odd-byte transfers aren't possible).
58 *
59 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
60 * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
61 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
62 *
63 */
64
65#define MAX_DMA_CHANNELS        8
66
67/* The maximum address that we can perform a DMA transfer to on this platform */
68#define MAX_DMA_ADDRESS      0x1000000
69
70/* 8237 DMA controllers */
71#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
72#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
73
74/* DMA controller registers */
75#define DMA1_CMD_REG            0x08    /* command register (w) */
76#define DMA1_STAT_REG           0x08    /* status register (r) */
77#define DMA1_REQ_REG            0x09    /* request register (w) */
78#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
79#define DMA1_MODE_REG           0x0B    /* mode register (w) */
80#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
81#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
82#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
83#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
84#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
85
86#define DMA2_CMD_REG            0xD0    /* command register (w) */
87#define DMA2_STAT_REG           0xD0    /* status register (r) */
88#define DMA2_REQ_REG            0xD2    /* request register (w) */
89#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
90#define DMA2_MODE_REG           0xD6    /* mode register (w) */
91#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
92#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
93#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
94#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
95#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
96
97#define DMA_ADDR_0              0x00    /* DMA address registers */
98#define DMA_ADDR_1              0x02
99#define DMA_ADDR_2              0x04
100#define DMA_ADDR_3              0x06
101#define DMA_ADDR_4              0xC0
102#define DMA_ADDR_5              0xC4
103#define DMA_ADDR_6              0xC8
104#define DMA_ADDR_7              0xCC
105
106#define DMA_CNT_0               0x01    /* DMA count registers */
107#define DMA_CNT_1               0x03
108#define DMA_CNT_2               0x05
109#define DMA_CNT_3               0x07
110#define DMA_CNT_4               0xC2
111#define DMA_CNT_5               0xC6
112#define DMA_CNT_6               0xCA
113#define DMA_CNT_7               0xCE
114
115#define DMA_PAGE_0              0x87    /* DMA page registers */
116#define DMA_PAGE_1              0x83
117#define DMA_PAGE_2              0x81
118#define DMA_PAGE_3              0x82
119#define DMA_PAGE_5              0x8B
120#define DMA_PAGE_6              0x89
121#define DMA_PAGE_7              0x8A
122
123#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
124#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
125#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
126
127/* enable/disable a specific DMA channel */
128static __inline__ void enable_dma(unsigned int dmanr)
129{
130        if (dmanr<=3)
131          {dma_outb(dmanr,  DMA1_MASK_REG);}
132        else
133          {dma_outb(dmanr & 3,  DMA2_MASK_REG);}
134}
135
136static __inline__ void disable_dma(unsigned int dmanr)
137{
138        if (dmanr<=3)
139          { dma_outb(dmanr | 4,  DMA1_MASK_REG); }
140        else
141          { dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);}
142}
143
144/* Clear the 'DMA Pointer Flip Flop'.
145 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
146 * Use this once to initialize the FF to a known state.
147 * After that, keep track of it. :-)
148 * --- In order to do that, the DMA routines below should ---
149 * --- only be used while interrupts are disabled! ---
150 */
151static __inline__ void clear_dma_ff(unsigned int dmanr)
152{
153        if (dmanr<=3)
154          {dma_outb(0,  DMA1_CLEAR_FF_REG);}
155        else
156          {dma_outb(0,  DMA2_CLEAR_FF_REG);}
157}
158
159/* set mode (above) for a specific DMA channel */
160static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
161{
162        if (dmanr<=3)
163          { dma_outb(mode | dmanr,  DMA1_MODE_REG);}
164        else
165          { dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);}
166}
167
168/* Set only the page register bits of the transfer address.
169 * This is used for successive transfers when we know the contents of
170 * the lower 16 bits of the DMA current address register, but a 64k boundary
171 * may have been crossed.
172 */
173static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
174{
175        switch(dmanr) {
176                case 0:
177                  {dma_outb(pagenr, DMA_PAGE_0);}
178                        break;
179                case 1:
180                  {dma_outb(pagenr, DMA_PAGE_1);}
181                        break;
182                case 2:
183                  {dma_outb(pagenr, DMA_PAGE_2);}
184                        break;
185                case 3:
186                  {dma_outb(pagenr, DMA_PAGE_3);}
187                        break;
188                case 5:
189                  {dma_outb(pagenr & 0xfe, DMA_PAGE_5);}
190                        break;
191                case 6:
192                  {dma_outb(pagenr & 0xfe, DMA_PAGE_6);}
193                        break;
194                case 7:
195                  {dma_outb(pagenr & 0xfe, DMA_PAGE_7);}
196                        break;
197        }
198}
199
200
201/* Set transfer address & page bits for specific DMA channel.
202 * Assumes dma flipflop is clear.
203 */
204static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
205{
206        set_dma_page(dmanr, a>>16);
207        if (dmanr <= 3)  {
208            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
209            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
210        }  else  {
211            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
212            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
213        }
214}
215
216
217/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
218 * a specific DMA channel.
219 * You must ensure the parameters are valid.
220 * NOTE: from a manual: "the number of transfers is one more
221 * than the initial word count"! This is taken into account.
222 * Assumes dma flip-flop is clear.
223 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
224 */
225static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
226{
227        count--;
228        if (dmanr <= 3)  {
229            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
230            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
231        } else {
232            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
233            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
234        }
235}
236
237
238/* Get DMA residue count. After a DMA transfer, this
239 * should return zero. Reading this while a DMA transfer is
240 * still in progress will return unpredictable results.
241 * If called before the channel has been used, it may return 1.
242 * Otherwise, it returns the number of _bytes_ left to transfer.
243 *
244 * Assumes DMA flip-flop is clear.
245 */
246static __inline__ int get_dma_residue(unsigned int dmanr)
247{
248        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
249                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
250
251        /* using short to get 16-bit wrap around */
252        unsigned short count,temp;
253
254        dma_inb(io_port,count);
255        count ++; 
256        dma_inb(io_port,temp);
257        count += temp << 8;
258       
259        return (dmanr<=3)? count : (count<<1);
260}
261
262
263
264
265#endif /* _ASM_DMA_H */
266
267
268
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