source: rtems/c/src/lib/libbsp/i386/force386/include/bsp.h @ ac7d5ef0

4.104.114.84.95
Last change on this file since ac7d5ef0 was ac7d5ef0, checked in by Joel Sherrill <joel.sherrill@…>, on May 11, 1995 at 5:39:37 PM

Initial revision

  • Property mode set to 100644
File size: 4.2 KB
Line 
1/*  bsp.h
2 *
3 *  This include file definitions related to the Force CPU-386 board.
4 *
5 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
6 *  On-Line Applications Research Corporation (OAR).
7 *  All rights assigned to U.S. Government, 1994.
8 *
9 *  This material may be reproduced by or for the U.S. Government pursuant
10 *  to the copyright license under the clause at DFARS 252.227-7013.  This
11 *  notice must appear in all copies of this file and its derivatives.
12 *
13 *  $Id$
14 */
15
16#ifndef __FORCE386_h
17#define __FORCE386_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#include <rtems.h>
24#include <iosupp.h>
25
26/*
27 *  Define the time limits for RTEMS Test Suite test durations.
28 *  Long test and short test duration limits are provided.  These
29 *  values are in seconds and need to be converted to ticks for the
30 *  application.
31 *
32 */
33
34#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
35#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
36
37/*
38 *  Define the interrupt mechanism for Time Test 27
39 *
40 *  NOTE: Use a software interrupt for the i386.
41 */
42
43#define MUST_WAIT_FOR_INTERRUTPT 0
44
45#define Install_tm27_vector( handler ) set_vector( (handler), 0x90, 1 )
46
47#define Cause_tm27_intr()              asm volatile( "int $0x90" : : );
48
49#define Clear_tm27_intr()
50
51#define Lower_tm27_intr()
52
53/*
54 *  Simple spin delay in microsecond units for device drivers.
55 *  This is very dependent on the clock speed of the target.
56 */
57
58#define delay( _microseconds ) \
59  { \
60    rtems_unsigned32 _counter; \
61    \
62    _counter = (_microseconds); \
63    \
64    asm volatile ( "0: nop;" \
65                   " mov %0,%0 ;" \
66                   " loop 0b" : "=c" (_counter) \
67                              : "0"  (_counter) \
68                 ); \
69    \
70  }
71
72/* Constants */
73
74#define RAM_START 0
75#define RAM_END   0x100000
76
77/* I/O addressing */
78
79/*
80 *  The following determines whether Port B or the Console should
81 *  be used for test I/O.  Setting ONE (and only ONE) of these to 1
82 *  enables I/O on that port.
83 *
84 *  PORT A - DUSCC MC68562 Channel A
85 *  PORT B - DUSCC MC68562 Channel B
86 *  PORT C - MFP MC68901 Channel      (*** FORCEbug console ***)
87 */
88
89#define PORTB         1               /* use port b as test port */
90#define PORTC         0               /* use console port as test port */
91
92#if ( PORTB == 1 )
93#define TX_STATUS     0x1b6           /* DUSCC General Status Register */
94#define RX_STATUS     0x1b6           /* DUSCC General Status Register */
95#define TX_BUFFER     0x1e0           /* DUSCC Transmitter Channel B */
96#define RX_BUFFER     0x1e8           /* DUSCC Receiver Channel B */
97#define Is_tx_ready( _status ) ( (_status) & 0x20 )
98#define Is_rx_ready( _status ) ( (_status) & 0x10 )
99#endif
100
101#if ( PORTC == 1 )
102#define TX_STATUS     0x12c           /* MFP Transmit Status Register */
103#define RX_STATUS     0x12a           /* MFP Receive Status Register */
104#define TX_BUFFER     0x12e           /* MFP Transmitter Channel  */
105#define RX_BUFFER     0x12e           /* MFP Receiver Channel  */
106#define Is_tx_ready( _status ) ( (_status) & 0x80 )
107#define Is_rx_ready( _status ) ( (_status) & 0x80 )
108#endif
109
110/* Timer constants */
111
112#define IERA   0x106     /* Interrupt Enable Register A */
113#define IMRA   0x112     /* Interrupt Mask Register A */
114#define TACR   0x118     /* Timer A Control Register */
115#define TADR   0x11e     /* Timer A Data Register */
116
117#define IERB   0x108     /* Interrupt Enable Register B */
118#define TBCR   0x11a     /* Timer B Control Register */
119#define TBDR   0x120     /* Timer B Data Register */
120
121/* Structures */
122
123#ifdef F386_INIT
124#undef BSP_EXTERN
125#define BSP_EXTERN
126#else
127#undef BSP_EXTERN
128#define BSP_EXTERN extern
129#endif
130
131/* miscellaneous stuff assumed to exist */
132
133extern rtems_configuration_table BSP_Configuration;
134
135extern i386_IDT_slot Interrupt_descriptor_table[ 256 ];
136extern i386_GDT_slot Global_descriptor_table[ 8192 ];
137
138BSP_EXTERN unsigned short Idt[3];  /* Interrupt Descriptor Table Address */
139BSP_EXTERN unsigned short Gdt[3];  /* Global Descriptor Table Address */
140BSP_EXTERN unsigned int   Idt_base;
141BSP_EXTERN unsigned int   Gdt_base;
142
143/* routines */
144
145i386_isr set_vector(
146  rtems_isr_entry     handler,
147  rtems_vector_number vector,
148  int                 type
149);
150
151#ifdef __cplusplus
152}
153#endif
154
155#endif
156/* end of include file */
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