1 | /* bsp.h |
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2 | * |
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3 | * This include file definitions related to the Force CPU-386 board. |
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4 | * |
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5 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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6 | * On-Line Applications Research Corporation (OAR). |
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7 | * All rights assigned to U.S. Government, 1994. |
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8 | * |
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9 | * This material may be reproduced by or for the U.S. Government pursuant |
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10 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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11 | * notice must appear in all copies of this file and its derivatives. |
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12 | * |
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13 | * $Id$ |
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14 | */ |
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15 | |
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16 | #ifndef __FORCE386_h |
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17 | #define __FORCE386_h |
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18 | |
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19 | #ifdef __cplusplus |
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20 | extern "C" { |
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21 | #endif |
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22 | |
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23 | #include <rtems.h> |
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24 | #include <iosupp.h> |
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25 | |
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26 | /* |
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27 | * Define the time limits for RTEMS Test Suite test durations. |
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28 | * Long test and short test duration limits are provided. These |
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29 | * values are in seconds and need to be converted to ticks for the |
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30 | * application. |
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31 | * |
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32 | */ |
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33 | |
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34 | #define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ |
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35 | #define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ |
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36 | |
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37 | /* |
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38 | * Define the interrupt mechanism for Time Test 27 |
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39 | * |
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40 | * NOTE: Use a software interrupt for the i386. |
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41 | */ |
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42 | |
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43 | #define MUST_WAIT_FOR_INTERRUTPT 0 |
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44 | |
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45 | #define Install_tm27_vector( handler ) set_vector( (handler), 0x90, 1 ) |
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46 | |
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47 | #define Cause_tm27_intr() asm volatile( "int $0x90" : : ); |
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48 | |
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49 | #define Clear_tm27_intr() |
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50 | |
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51 | #define Lower_tm27_intr() |
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52 | |
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53 | /* |
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54 | * Simple spin delay in microsecond units for device drivers. |
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55 | * This is very dependent on the clock speed of the target. |
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56 | */ |
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57 | |
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58 | #define delay( _microseconds ) \ |
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59 | { \ |
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60 | rtems_unsigned32 _counter; \ |
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61 | \ |
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62 | _counter = (_microseconds); \ |
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63 | \ |
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64 | asm volatile ( "0: nop;" \ |
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65 | " mov %0,%0 ;" \ |
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66 | " loop 0b" : "=c" (_counter) \ |
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67 | : "0" (_counter) \ |
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68 | ); \ |
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69 | \ |
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70 | } |
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71 | |
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72 | /* Constants */ |
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73 | |
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74 | #define RAM_START 0 |
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75 | #define RAM_END 0x100000 |
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76 | |
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77 | /* I/O addressing */ |
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78 | |
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79 | /* |
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80 | * The following determines whether Port B or the Console should |
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81 | * be used for test I/O. Setting ONE (and only ONE) of these to 1 |
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82 | * enables I/O on that port. |
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83 | * |
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84 | * PORT A - DUSCC MC68562 Channel A |
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85 | * PORT B - DUSCC MC68562 Channel B |
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86 | * PORT C - MFP MC68901 Channel (*** FORCEbug console ***) |
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87 | */ |
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88 | |
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89 | #define PORTB 1 /* use port b as test port */ |
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90 | #define PORTC 0 /* use console port as test port */ |
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91 | |
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92 | #if ( PORTB == 1 ) |
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93 | #define TX_STATUS 0x1b6 /* DUSCC General Status Register */ |
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94 | #define RX_STATUS 0x1b6 /* DUSCC General Status Register */ |
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95 | #define TX_BUFFER 0x1e0 /* DUSCC Transmitter Channel B */ |
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96 | #define RX_BUFFER 0x1e8 /* DUSCC Receiver Channel B */ |
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97 | #define Is_tx_ready( _status ) ( (_status) & 0x20 ) |
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98 | #define Is_rx_ready( _status ) ( (_status) & 0x10 ) |
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99 | #endif |
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100 | |
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101 | #if ( PORTC == 1 ) |
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102 | #define TX_STATUS 0x12c /* MFP Transmit Status Register */ |
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103 | #define RX_STATUS 0x12a /* MFP Receive Status Register */ |
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104 | #define TX_BUFFER 0x12e /* MFP Transmitter Channel */ |
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105 | #define RX_BUFFER 0x12e /* MFP Receiver Channel */ |
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106 | #define Is_tx_ready( _status ) ( (_status) & 0x80 ) |
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107 | #define Is_rx_ready( _status ) ( (_status) & 0x80 ) |
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108 | #endif |
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109 | |
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110 | /* Timer constants */ |
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111 | |
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112 | #define IERA 0x106 /* Interrupt Enable Register A */ |
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113 | #define IMRA 0x112 /* Interrupt Mask Register A */ |
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114 | #define TACR 0x118 /* Timer A Control Register */ |
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115 | #define TADR 0x11e /* Timer A Data Register */ |
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116 | |
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117 | #define IERB 0x108 /* Interrupt Enable Register B */ |
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118 | #define TBCR 0x11a /* Timer B Control Register */ |
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119 | #define TBDR 0x120 /* Timer B Data Register */ |
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120 | |
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121 | /* Structures */ |
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122 | |
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123 | #ifdef F386_INIT |
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124 | #undef BSP_EXTERN |
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125 | #define BSP_EXTERN |
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126 | #else |
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127 | #undef BSP_EXTERN |
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128 | #define BSP_EXTERN extern |
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129 | #endif |
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130 | |
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131 | /* miscellaneous stuff assumed to exist */ |
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132 | |
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133 | extern rtems_configuration_table BSP_Configuration; |
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134 | |
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135 | extern i386_IDT_slot Interrupt_descriptor_table[ 256 ]; |
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136 | extern i386_GDT_slot Global_descriptor_table[ 8192 ]; |
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137 | |
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138 | BSP_EXTERN unsigned short Idt[3]; /* Interrupt Descriptor Table Address */ |
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139 | BSP_EXTERN unsigned short Gdt[3]; /* Global Descriptor Table Address */ |
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140 | BSP_EXTERN unsigned int Idt_base; |
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141 | BSP_EXTERN unsigned int Gdt_base; |
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142 | |
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143 | /* routines */ |
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144 | |
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145 | i386_isr_entry set_vector( |
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146 | rtems_isr_entry handler, |
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147 | rtems_vector_number vector, |
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148 | int type |
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149 | ); |
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150 | |
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151 | #ifdef __cplusplus |
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152 | } |
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153 | #endif |
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154 | |
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155 | #endif |
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156 | /* end of include file */ |
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