1 | /* bspstart.c for eZKit533 |
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2 | * |
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3 | * This routine starts the application. It includes application, |
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4 | * board, and monitor specific initialization and configuration. |
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5 | * The generic CPU dependent initialization has been performed |
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6 | * before this routine is invoked. |
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7 | * |
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8 | * Copyright (c) 2006 by Atos Automacao Industrial Ltda. |
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9 | * written by Alain Schaefer <alain.schaefer@easc.ch> |
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10 | * and Antonio Giovanini <antonio@atos.com.br> |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.com/license/LICENSE. |
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15 | * |
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16 | * $Id$ |
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17 | */ |
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18 | |
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19 | |
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20 | #include <bsp.h> |
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21 | #include <cplb.h> |
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22 | #include <libcpu/interrupt.h> |
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23 | |
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24 | const unsigned int dcplbs_table[16][2] = { |
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25 | { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, |
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26 | { 0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, /* L1 Data B */ |
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27 | { 0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, /* L1 Data A */ |
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28 | { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, |
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29 | { 0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 3 */ |
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30 | { 0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 2 (Secnd) */ |
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31 | { 0x20100000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 1 (Prim B) */ |
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32 | { 0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 0 (Prim A) */ |
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33 | |
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34 | { 0x02400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, |
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35 | { 0x02000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, |
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36 | { 0x00C00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, |
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37 | { 0x00800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, |
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38 | { 0x00400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, |
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39 | { 0x00000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, |
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40 | { 0xffffffff, 0xffffffff } /* end of section - termination */ |
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41 | |
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42 | }; |
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43 | |
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44 | |
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45 | const unsigned int _icplbs_table[16][2] = { |
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46 | { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) }, /* L1 Code */ |
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47 | { 0xEF000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* AREA DE BOOT */ |
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48 | { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, |
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49 | { 0x20300000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 3 */ |
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50 | { 0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 2 (Secnd) */ |
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51 | { 0x20100000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 1 (Prim B) */ |
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52 | { 0x20000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 0 (Prim A) */ |
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53 | |
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54 | { 0x02400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, |
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55 | { 0x02000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, |
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56 | { 0x00C00000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, |
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57 | { 0x00800000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, |
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58 | { 0x00400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, |
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59 | { 0x00000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, |
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60 | { 0xffffffff, 0xffffffff } /* end of section - termination */ |
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61 | |
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62 | }; |
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63 | |
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64 | /* |
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65 | * Use the shared implementations of the following routines |
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66 | */ |
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67 | |
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68 | void Init_PLL (void); |
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69 | void Init_EBIU (void); |
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70 | void Init_Flags(void); |
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71 | void Init_RTC (void); |
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72 | |
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73 | void null_isr(void); |
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74 | |
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75 | /* |
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76 | * BSP pretasking hook. Called just before drivers are initialized. |
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77 | * Used to setup libc and install any BSP extensions. |
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78 | */ |
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79 | |
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80 | void bsp_pretasking_hook(void) |
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81 | { |
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82 | bfin_interrupt_init(); |
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83 | } |
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84 | |
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85 | /* |
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86 | * bsp_start |
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87 | * |
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88 | * This routine does the bulk of the system initialization. |
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89 | */ |
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90 | |
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91 | void bsp_start( void ) |
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92 | { |
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93 | /* BSP Hardware Initialization*/ |
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94 | Init_RTC(); /* Blackfin Real Time Clock initialization */ |
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95 | Init_PLL(); /* PLL initialization */ |
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96 | Init_EBIU(); /* EBIU initialization */ |
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97 | Init_Flags(); /* GPIO initialization */ |
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98 | |
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99 | int i=0; |
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100 | for (i=5;i<16;i++) { |
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101 | set_vector((rtems_isr_entry)null_isr, i, 1); |
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102 | } |
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103 | } |
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104 | |
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105 | /* |
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106 | * Init_PLL |
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107 | * |
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108 | * Routine to initialize the PLL. The Ezkit uses a 27 Mhz XTAL. |
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109 | * See "../eZKit533/include/bsp.h" for more information. |
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110 | */ |
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111 | void Init_PLL (void) |
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112 | { |
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113 | unsigned int n; |
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114 | |
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115 | /* Configure PLL registers */ |
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116 | *((uint16_t*)PLL_LOCKCNT) = 0x1000; |
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117 | *((uint16_t*)PLL_DIV) = PLL_CSEL|PLL_SSEL; |
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118 | *((uint16_t*)PLL_CTL) = PLL_MSEL|PLL_DF; |
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119 | |
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120 | /* Commands to set PLL values */ |
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121 | asm("cli r0;"); |
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122 | asm("idle;"); |
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123 | asm("sti r0;"); |
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124 | |
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125 | /* Delay for PLL stabilization */ |
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126 | for (n=0; n<200; n++) {} |
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127 | } |
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128 | |
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129 | /* |
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130 | * Init_EBIU |
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131 | * |
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132 | * Configure extern memory |
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133 | */ |
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134 | |
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135 | void Init_EBIU (void) |
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136 | { |
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137 | /* Configure FLASH */ |
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138 | *((uint32_t*)EBIU_AMBCTL0) = 0x7bb07bb0L; |
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139 | *((uint32_t*)EBIU_AMBCTL1) = 0x7bb07bb0L; |
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140 | *((uint16_t*)EBIU_AMGCTL) = 0x000f; |
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141 | |
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142 | /* Configure SDRAM |
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143 | *((uint32_t*)EBIU_SDGCTL) = 0x0091998d; |
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144 | *((uint16_t*)EBIU_SDBCTL) = 0x0013; |
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145 | *((uint16_t*)EBIU_SDRRC) = 0x0817; |
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146 | */ |
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147 | } |
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148 | |
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149 | /* |
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150 | * Init_Flags |
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151 | * |
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152 | * Enable LEDs port |
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153 | */ |
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154 | void Init_Flags(void) |
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155 | { |
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156 | *((uint16_t*)FIO_INEN) = 0x0100; |
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157 | *((uint16_t*)FIO_DIR) = 0x0000; |
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158 | *((uint16_t*)FIO_EDGE) = 0x0100; |
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159 | *((uint16_t*)FIO_MASKA_D) = 0x0100; |
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160 | |
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161 | *((uint8_t*)FlashA_PortB_Dir) = 0x3f; |
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162 | *((uint8_t*)FlashA_PortB_Data) = 0x00; |
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163 | } |
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164 | |
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165 | /* |
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166 | * Helper Function to use the EzKits LEDS. |
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167 | * Can be used by the Application. |
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168 | */ |
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169 | void setLED (uint8_t value) |
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170 | { |
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171 | *((uint8_t*)FlashA_PortB_Data) = value; |
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172 | } |
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173 | |
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174 | /* |
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175 | * Helper Function to use the EzKits LEDS |
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176 | */ |
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177 | uint8_t getLED (void) |
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178 | { |
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179 | return *((uint8_t*)FlashA_PortB_Data); |
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180 | } |
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181 | |
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182 | void initCPLB(void) |
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183 | { |
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184 | int i = 0; |
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185 | unsigned int *addr; |
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186 | unsigned int *data; |
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187 | |
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188 | addr = (unsigned int *)0xffe00100; |
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189 | data = (unsigned int *)0xffe00200; |
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190 | |
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191 | while ( dcplbs_table[i][0] != 0xffffffff ) { |
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192 | *addr = dcplbs_table[i][0]; |
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193 | *data = dcplbs_table[i][1]; |
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194 | addr++; |
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195 | data++; |
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196 | } |
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197 | } |
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