source: rtems/c/src/lib/libbsp/bfin/eZKit533/startup/bspstart.c @ 27d33ed

4.104.114.84.95
Last change on this file since 27d33ed was 27d33ed, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 10, 2007 at 1:55:06 PM

2007-09-10 Alain Schaefer <alani@…>

  • startup/bspstart.c: Add a useful routine to program memory protection in bfin. It is not used but a user of ezKit533 can customize its bsp and use this function.
  • Property mode set to 100644
File size: 7.1 KB
Line 
1/*  bspstart.c for eZKit533
2 *
3 *  This routine starts the application.  It includes application,
4 *  board, and monitor specific initialization and configuration.
5 *  The generic CPU dependent initialization has been performed
6 *  before this routine is invoked.
7 * 
8 *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
9 *             written by Alain Schaefer <alain.schaefer@easc.ch>
10 *                    and Antonio Giovanini <antonio@atos.com.br>
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19
20#include <string.h>
21
22#include <bsp.h>
23#include <rtems/libio.h>
24#include <rtems/libcsupport.h>
25
26
27/*
28 *  The original table from the application and our copy of it with
29 *  some changes.
30 */
31
32extern rtems_configuration_table Configuration;
33
34rtems_configuration_table  BSP_Configuration;
35
36rtems_cpu_table Cpu_table;
37
38char *rtems_progname;
39
40
41const unsigned int dcplbs_table[][] = { 
42
43       { 0xFF900000,   (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, // L1 Data B
44       { 0xFF800000,   (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, // L1 Data A
45
46       { 0x20300000,   (PAGE_SIZE_1MB | CPLB_DNOCACHE) },      // Async Memory Bank 3
47       { 0x20200000,   (PAGE_SIZE_1MB | CPLB_DNOCACHE) },      // Async Memory Bank 2 (Secnd)
48       { 0x20100000,   (PAGE_SIZE_1MB | CPLB_DNOCACHE) },      // Async Memory Bank 1 (Prim B)
49       { 0x20000000,   (PAGE_SIZE_1MB | CPLB_DNOCACHE) },      // Async Memory Bank 0 (Prim A)
50
51       { 0x02400000,   (PAGE_SIZE_4MB | CPLB_DNOCACHE) },      //
52       { 0x02000000,   (PAGE_SIZE_4MB | CPLB_DNOCACHE) },      //
53       { 0x00C00000,   (PAGE_SIZE_4MB | CPLB_DNOCACHE) },      //
54       { 0x00800000,   (PAGE_SIZE_4MB | CPLB_DNOCACHE) },      //
55       { 0x00400000,   (PAGE_SIZE_4MB | CPLB_DNOCACHE) },      //
56       { 0x00000000,   (PAGE_SIZE_4MB | CPLB_DNOCACHE) },      //
57
58       { 0xffffffff, 0xffffffff }                                                      // end of section - termination
59
60       }
61;
62
63
64const unsigned int _icplbs_table[][] = { 
65       { 0xFFA00000,   (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT) },   // L1 Code
66
67       { 0xEF000000,   (PAGE_SIZE_1MB | CPLB_INOCACHE) },      // AREA DE BOOT
68
69       { 0x20300000,   (PAGE_SIZE_1MB | CPLB_INOCACHE) },      // Async Memory Bank 3
70       { 0x20200000,   (PAGE_SIZE_1MB | CPLB_INOCACHE) },      // Async Memory Bank 2 (Secnd)
71       { 0x20100000,   (PAGE_SIZE_1MB | CPLB_INOCACHE) },      // Async Memory Bank 1 (Prim B)
72       { 0x20000000,   (PAGE_SIZE_1MB | CPLB_INOCACHE) },      // Async Memory Bank 0 (Prim A)
73
74       { 0x02400000,   (PAGE_SIZE_4MB | CPLB_INOCACHE) },      //
75       { 0x02000000,   (PAGE_SIZE_4MB | CPLB_INOCACHE) },      //
76       { 0x00C00000,   (PAGE_SIZE_4MB | CPLB_INOCACHE) },      //
77       { 0x00800000,   (PAGE_SIZE_4MB | CPLB_INOCACHE) },      //
78       { 0x00400000,   (PAGE_SIZE_4MB | CPLB_INOCACHE) },      //
79       { 0x00000000,   (PAGE_SIZE_4MB | CPLB_INOCACHE) },      //
80
81       { 0xffffffff, 0xffffffff  }                                                     // end of section - termination
82
83       }
84;
85
86/*
87 *  Use the shared implementations of the following routines
88 */
89
90void bsp_postdriver_hook(void);
91void bsp_libc_init( void *, uint32_t, int );
92void Init_PLL (void);
93void Init_EBIU (void);
94void Init_Flags(void);
95void Init_RTC (void);
96
97void null_isr(void);
98
99/*
100 *  Function:   bsp_pretasking_hook
101 *  Created:    95/03/10
102 *
103 *  Description:
104 *      BSP pretasking hook.  Called just before drivers are initialized.
105 *      Used to setup libc and install any BSP extensions.
106 *
107 *  NOTES:
108 *      Must not use libc (to do io) from here, since drivers are
109 *      not yet initialized.
110 *
111 */
112
113void bsp_pretasking_hook(void)
114{
115    extern int HeapBase;
116    extern int HeapSize;
117    void         *heapStart = &HeapBase;
118    unsigned long heapSize = (unsigned long)&HeapSize;
119
120    bsp_libc_init(heapStart, heapSize, 0);
121
122#ifdef RTEMS_DEBUG
123    rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
124#endif
125}
126
127/*
128 *  bsp_start
129 *
130 *  This routine does the bulk of the system initialization.
131 */
132
133void bsp_start( void )
134{
135   
136  extern void          * _WorkspaceBase;
137
138  /* BSP Hardware Initialization*/
139  Init_RTC();   /* Blackfin Real Time Clock initialization */ 
140  Init_PLL();   /* PLL initialization */
141  Init_EBIU();  /* EBIU initialization */
142  Init_Flags(); /* GPIO initialization */
143
144  /*
145   *  Allocate the memory for the RTEMS Work Space.  This can come from
146   *  a variety of places: hard coded address, malloc'ed from outside
147   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
148   *  typically done by stock BSPs) by subtracting the required amount
149   *  of work space from the last physical address on the CPU board.
150   */
151
152  /*
153   *  Need to "allocate" the memory for the RTEMS Workspace and
154   *  tell the RTEMS configuration where it is.  This memory is
155   *  not malloc'ed.  It is just "pulled from the air".
156   */
157
158  BSP_Configuration.work_space_start = (void *) &_WorkspaceBase;
159
160  /*
161   *  initialize the CPU table for this BSP
162   */
163
164  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
165  Cpu_table.postdriver_hook = bsp_postdriver_hook;
166  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
167
168  int i=0;
169  for (i=5;i<16;i++) {
170    set_vector((rtems_isr_entry)null_isr, i, 1);
171  }
172 
173}
174
175 /*
176  * Init_PLL
177  *
178  * Routine to initialize the PLL. The Ezkit uses a 27 Mhz XTAL.
179  * See "../eZKit533/include/bsp.h" for more information.
180  */
181
182void Init_PLL (void)
183{
184 
185  unsigned int n;
186 
187  /* Configure PLL registers */
188  *((uint16_t*)PLL_LOCKCNT) = 0x1000;
189  *((uint16_t*)PLL_DIV) = PLL_CSEL|PLL_SSEL;
190  *((uint16_t*)PLL_CTL) = PLL_MSEL|PLL_DF;
191
192  /* Commands to set PLL values */
193  asm("cli r0;");
194  asm("idle;");
195  asm("sti r0;");
196 
197  /* Delay for PLL stabilization */
198  for (n=0; n<200; n++) {} 
199 
200}
201
202 /*
203  * Init_EBIU
204  *
205  * Configure extern memory
206  */
207
208void Init_EBIU (void)
209{
210  /* Configure FLASH */
211  *((uint32_t*)EBIU_AMBCTL0)  = 0x7bb07bb0L;
212  *((uint32_t*)EBIU_AMBCTL1)  = 0x7bb07bb0L;
213  *((uint16_t*)EBIU_AMGCTL)   = 0x000f;
214 
215  /* Configure SDRAM
216  *((uint32_t*)EBIU_SDGCTL) = 0x0091998d;
217  *((uint16_t*)EBIU_SDBCTL) = 0x0013;
218  *((uint16_t*)EBIU_SDRRC)  = 0x0817;
219  */
220}
221
222 /*
223  * Init_Flags
224  *
225  * Enable LEDs port
226  */
227void Init_Flags(void)
228{
229  *((uint16_t*)FIO_INEN)    = 0x0100;
230  *((uint16_t*)FIO_DIR)     = 0x0000;
231  *((uint16_t*)FIO_EDGE)    = 0x0100;
232  *((uint16_t*)FIO_MASKA_D) = 0x0100;
233 
234  *((uint8_t*)FlashA_PortB_Dir)  = 0x3f;
235  *((uint8_t*)FlashA_PortB_Data) = 0x00;   
236}
237
238/*
239 * Helper Function to use the EzKits LEDS.
240 * Can be used by the Application.
241 */
242void setLED (uint8_t value)
243{
244  *((uint8_t*)FlashA_PortB_Data) = value;   
245}
246
247/*
248 * Helper Function to use the EzKits LEDS
249 */
250uint8_t getLED (void)
251{
252  return *((uint8_t*)FlashA_PortB_Data);
253}
254
255void initCPLB() {
256
257       int i = 0;
258       unsigned int *addr;
259       unsigned int *data;
260       
261       addr = 0xffe00100;
262       data = 0xffe00200;
263
264       while ( dcplbs_table[i][0] != 0xffffffff ) {
265               *addr = dcplbs_table[i][0];
266               *data = dcplbs_table[i][1];
267
268               addr++;
269               data++;
270       } 
271}
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