source: rtems/c/src/lib/libbsp/bfin/bf537Stamp/startup/bspstart.c @ ed6365a

4.115
Last change on this file since ed6365a was ed6365a, checked in by Joel Sherrill <joel.sherrill@…>, on 10/14/14 at 16:03:38

bfin libcpu and libbsp: Fix warnings

  • Property mode set to 100644
File size: 8.1 KB
Line 
1/*  bspstart.c for bf537Stamp
2 *
3 *  This routine does the bulk of the system initialisation.
4 */
5
6/*
7 *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
8 *             written by Alain Schaefer <alain.schaefer@easc.ch>
9 *                    and Antonio Giovanini <antonio@atos.com.br>
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.org/license/LICENSE.
14 */
15
16
17#include <bsp.h>
18#include <bsp/bootcard.h>
19#include <libcpu/bf537.h>
20#include <libcpu/ebiuRegs.h>
21#include <libcpu/gpioRegs.h>
22#include <libcpu/mmu.h>
23#include <libcpu/mmuRegs.h>
24#include <libcpu/interrupt.h>
25
26
27static bfin_mmu_config_t mmuRegions = {
28    /* instruction */
29    {
30        {(void *) 0x00000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
31        {(void *) 0x00400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
32        {(void *) 0x00800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
33        {(void *) 0x00c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
34        {(void *) 0x01000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
35        {(void *) 0x01400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
36        {(void *) 0x01800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
37        {(void *) 0x01c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
38        {(void *) 0x02000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
39        {(void *) 0x02400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
40        {(void *) 0x02800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
41        {(void *) 0x02c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
42        {(void *) 0x03000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
43        {(void *) 0x20000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
44        {(void *) 0xff800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE},
45        {(void *) 0xffc00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE}
46    },
47    /* data */
48    {
49        {(void *) 0x00000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
50        {(void *) 0x00400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
51        {(void *) 0x00800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
52        {(void *) 0x00c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
53        {(void *) 0x01000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
54        {(void *) 0x01400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
55        {(void *) 0x01800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
56        {(void *) 0x01c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
57        {(void *) 0x02000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
58        {(void *) 0x02400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
59        {(void *) 0x02800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
60        {(void *) 0x02c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
61        {(void *) 0x03000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
62        {(void *) 0x20000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
63        {(void *) 0xff800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE},
64        {(void *) 0xffc00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE}
65    }
66};
67
68static void initPLL(void);
69static void initEBIU(void);
70static void initGPIO(void);
71
72/*
73 *  BSP pretasking hook.
74 */
75void bsp_pretasking_hook(void)
76{
77  bfin_interrupt_init();
78}
79
80void bsp_start(void)
81{
82  /* BSP Hardware Initialization*/
83
84  *(uint32_t volatile *) DMEM_CONTROL |= DMEM_CONTROL_PORT_PREF0;
85  *(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_PORT_PREF1;
86  bfin_mmu_init(&mmuRegions);
87  rtems_cache_enable_instruction();
88  rtems_cache_enable_data();
89
90  Init_RTC();   /* Blackfin Real Time Clock initialization */
91
92  initPLL();   /* PLL initialization */
93  initEBIU();  /* EBIU initialization */
94  initGPIO();  /* GPIO initialization */
95}
96
97 /*
98  * initPLL
99  *
100  * Routine to initialize the PLL. The BF537 Stamp uses a 27 Mhz XTAL. BISON
101  * See "../bf537Stamp/include/bsp.h" for more information.
102  */
103
104static void initPLL(void) {
105
106#ifdef BISON
107  unsigned int n;
108
109  /* Configure PLL registers */
110  *((uint16_t*)PLL_LOCKCNT) = 0x1000;
111  *((uint16_t*)PLL_DIV) = PLL_CSEL|PLL_SSEL;
112  *((uint16_t*)PLL_CTL) = PLL_MSEL|PLL_DF;
113
114  /* Commands to set PLL values */
115  __asm__ ("cli r0;");
116  __asm__ ("idle;");
117  __asm__ ("sti r0;");
118
119  /* Delay for PLL stabilization */
120  for (n=0; n<200; n++) {}
121#endif
122
123}
124
125 /*
126  * initEBIU
127  *
128  * Configure extern memory
129  */
130
131static void initEBIU(void) {
132
133  /* by default the processor has priority over dma channels for access to
134     external memory.  this has been seen to result in dma unerruns on
135     ethernet transmit; it seems likely it could cause dma overruns on
136     ethernet receive as well.  setting the following bit gives the dma
137     channels priority over the cpu, fixing that problem.  unfortunately
138     we don't have finer grain control than that; all dma channels now
139     have priority over the cpu. */
140  *(uint16_t volatile *) EBIU_AMGCTL |= EBIU_AMGCTL_CDPRIO;
141
142#ifdef BISON
143  /* Configure FLASH */
144  *((uint32_t*)EBIU_AMBCTL0)  = 0x7bb07bb0L;
145  *((uint32_t*)EBIU_AMBCTL1)  = 0x7bb07bb0L;
146  *((uint16_t*)EBIU_AMGCTL)   = 0x000f;
147
148  /* Configure SDRAM
149  *((uint32_t*)EBIU_SDGCTL) = 0x0091998d;
150  *((uint16_t*)EBIU_SDBCTL) = 0x0013;
151  *((uint16_t*)EBIU_SDRRC)  = 0x0817;
152  */
153#endif
154}
155
156 /*
157  * initGPIO
158  *
159  * Enable LEDs port
160  */
161static void initGPIO(void) {
162#if (!BFIN_ON_SKYEYE)
163  *(uint16_t volatile *) PORT_MUX = 0;
164
165  /* port f bits 0, 1: uart0 tx, rx */
166  /*        bits 2 - 5: buttons */
167  /*        bits 6 - 11: leds */
168  *(uint16_t volatile *) PORTF_FER = 0x0003;
169  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000;
170  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x003c;
171  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000;
172  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000;
173  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000;
174  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000;
175  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000;
176  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0fc0;
177
178  *(uint16_t volatile *) PORTG_FER = 0x0000;
179  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000;
180  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x0000;
181  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000;
182  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000;
183  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000;
184  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000;
185  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000;
186  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0000;
187
188  /* port h bits 0 - 15: ethernet */
189  *(uint16_t volatile *) PORTH_FER = 0xffff;
190  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000;
191  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x0000;
192  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000;
193  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000;
194  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000;
195  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000;
196  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000;
197  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0000;
198#endif
199}
200
201/*
202 * Helper Function to use the EzKits LEDS.
203 * Can be used by the Application.
204 */
205void setLEDs(uint8_t value) {
206
207  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_CLEAR_OFFSET) =
208      (uint16_t) (~value & 0x3f) << 6;
209  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_SET_OFFSET) =
210      (uint16_t) (value & 0x3f) << 6;
211}
212
213/*
214 * Helper Function to use the EzKits LEDS
215 */
216uint8_t getLEDs(void) {
217  uint16_t r;
218
219  r = *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET);
220  return (uint8_t) ((r >> 6) & 0x3f);
221}
222
223uint8_t getButtons(void) {
224  uint16_t r;
225
226  r = *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET);
227
228  return (uint8_t) ((r >> 2) & 0x0f);
229}
230
231
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