source: rtems/c/src/lib/libbsp/bfin/bf537Stamp/startup/bspstart.c @ 64501892

4.104.11
Last change on this file since 64501892 was 64501892, checked in by Joel Sherrill <joel.sherrill@…>, on May 27, 2009 at 11:58:16 AM

2009-05-25 Allan Hessenflow <allanh@…>

PR 1415/bsps

  • startup/bspstart.c, startup/linkcmds: Enable caches and therefore enable the mmu.
  • start/start.S: Correct call to boot_card to meet bfin abi by clearing l0 - l3 and allocating some stack space.
  • Property mode set to 100644
File size: 8.4 KB
Line 
1/*  bspstart.c for bf537Stamp
2 *
3 *  This routine starts the application.  It includes application,
4 *  board, and monitor specific initialization and configuration.
5 *  The generic CPU dependent initialization has been performed
6 *  before this routine is invoked.
7 * 
8 *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
9 *             written by Alain Schaefer <alain.schaefer@easc.ch>
10 *                    and Antonio Giovanini <antonio@atos.com.br>
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19
20#include <bsp.h>
21#include <libcpu/bf537.h>
22#include <libcpu/ebiuRegs.h>
23#include <libcpu/gpioRegs.h>
24#include <libcpu/mmu.h>
25#include <libcpu/mmuRegs.h>
26#include <libcpu/interrupt.h>
27
28
29static bfin_mmu_config_t mmuRegions = {
30    /* instruction */
31    {
32        {(void *) 0x00000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
33        {(void *) 0x00400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
34        {(void *) 0x00800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
35        {(void *) 0x00c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
36        {(void *) 0x01000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
37        {(void *) 0x01400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
38        {(void *) 0x01800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
39        {(void *) 0x01c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
40        {(void *) 0x02000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
41        {(void *) 0x02400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
42        {(void *) 0x02800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
43        {(void *) 0x02c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
44        {(void *) 0x03000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
45        {(void *) 0x20000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
46        {(void *) 0xff800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE},
47        {(void *) 0xffc00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE}
48    },
49    /* data */
50    {
51        {(void *) 0x00000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
52        {(void *) 0x00400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
53        {(void *) 0x00800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
54        {(void *) 0x00c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
55        {(void *) 0x01000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
56        {(void *) 0x01400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
57        {(void *) 0x01800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
58        {(void *) 0x01c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
59        {(void *) 0x02000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
60        {(void *) 0x02400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
61        {(void *) 0x02800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
62        {(void *) 0x02c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
63        {(void *) 0x03000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
64        {(void *) 0x20000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
65        {(void *) 0xff800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE},
66        {(void *) 0xffc00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE}
67    }
68};
69
70void Init_RTC(void);
71
72static void initPLL(void);
73static void initEBIU(void);
74static void initGPIO(void);
75
76/*
77 *  BSP pretasking hook.
78 */
79void bsp_pretasking_hook(void)
80{
81  bfin_interrupt_init();
82}
83
84/*
85 *  bsp_start
86 *
87 *  This routine does the bulk of the BSP initialization.
88 */
89void bsp_start(void)
90{
91  /* BSP Hardware Initialization*/
92
93  *(uint32_t volatile *) DMEM_CONTROL |= DMEM_CONTROL_PORT_PREF0;
94  *(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_PORT_PREF1;
95  bfin_mmu_init(&mmuRegions);
96  rtems_cache_enable_instruction();
97  rtems_cache_enable_data();
98
99  Init_RTC();   /* Blackfin Real Time Clock initialization */
100
101  initPLL();   /* PLL initialization */
102  initEBIU();  /* EBIU initialization */
103  initGPIO();  /* GPIO initialization */
104}
105
106 /*
107  * initPLL
108  *
109  * Routine to initialize the PLL. The BF537 Stamp uses a 27 Mhz XTAL. BISON
110  * See "../bf537Stamp/include/bsp.h" for more information.
111  */
112
113static void initPLL(void) {
114 
115#ifdef BISON
116  unsigned int n;
117 
118  /* Configure PLL registers */
119  *((uint16_t*)PLL_LOCKCNT) = 0x1000;
120  *((uint16_t*)PLL_DIV) = PLL_CSEL|PLL_SSEL;
121  *((uint16_t*)PLL_CTL) = PLL_MSEL|PLL_DF;
122
123  /* Commands to set PLL values */
124  asm("cli r0;");
125  asm("idle;");
126  asm("sti r0;");
127 
128  /* Delay for PLL stabilization */
129  for (n=0; n<200; n++) {} 
130#endif
131 
132}
133
134 /*
135  * initEBIU
136  *
137  * Configure extern memory
138  */
139
140static void initEBIU(void) {
141
142  /* by default the processor has priority over dma channels for access to
143     external memory.  this has been seen to result in dma unerruns on
144     ethernet transmit; it seems likely it could cause dma overruns on
145     ethernet receive as well.  setting the following bit gives the dma
146     channels priority over the cpu, fixing that problem.  unfortunately
147     we don't have finer grain control than that; all dma channels now
148     have priority over the cpu. */
149  *(uint16_t volatile *) EBIU_AMGCTL |= EBIU_AMGCTL_CDPRIO;
150
151#ifdef BISON
152  /* Configure FLASH */
153  *((uint32_t*)EBIU_AMBCTL0)  = 0x7bb07bb0L;
154  *((uint32_t*)EBIU_AMBCTL1)  = 0x7bb07bb0L;
155  *((uint16_t*)EBIU_AMGCTL)   = 0x000f;
156 
157  /* Configure SDRAM
158  *((uint32_t*)EBIU_SDGCTL) = 0x0091998d;
159  *((uint16_t*)EBIU_SDBCTL) = 0x0013;
160  *((uint16_t*)EBIU_SDRRC)  = 0x0817;
161  */
162#endif
163}
164
165 /*
166  * initGPIO
167  *
168  * Enable LEDs port
169  */
170static void initGPIO(void) {
171#if (!BFIN_ON_SKYEYE)
172  *(uint16_t volatile *) PORT_MUX = 0;
173
174  /* port f bits 0, 1: uart0 tx, rx */
175  /*        bits 2 - 5: buttons */
176  /*        bits 6 - 11: leds */
177  *(uint16_t volatile *) PORTF_FER = 0x0003;
178  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000;
179  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x003c;
180  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000;
181  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000;
182  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000;
183  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000;
184  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000;
185  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0fc0;
186
187  *(uint16_t volatile *) PORTG_FER = 0x0000;
188  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000;
189  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x0000;
190  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000;
191  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000;
192  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000;
193  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000;
194  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000;
195  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0000;
196
197  /* port h bits 0 - 15: ethernet */
198  *(uint16_t volatile *) PORTH_FER = 0xffff;
199  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000;
200  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x0000;
201  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000;
202  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000;
203  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000;
204  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000;
205  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000;
206  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0000;
207#endif
208}
209
210/*
211 * Helper Function to use the EzKits LEDS.
212 * Can be used by the Application.
213 */
214void setLEDs(uint8_t value) {
215
216  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_CLEAR_OFFSET) =
217      (uint16_t) (~value & 0x3f) << 6;
218  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_SET_OFFSET) =
219      (uint16_t) (value & 0x3f) << 6;
220}
221
222/*
223 * Helper Function to use the EzKits LEDS
224 */
225uint8_t getLEDs(void) {
226  uint16_t r;
227
228  r = *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET);
229  return (uint8_t) ((r >> 6) & 0x3f);
230}
231
232uint8_t getButtons(void) {
233  uint16_t r;
234
235  r = *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET);
236
237  return (uint8_t) ((r >> 2) & 0x0f);
238}
239
240
Note: See TracBrowser for help on using the repository browser.