1 | /* bspstart.c for bf537Stamp |
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2 | * |
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3 | * This routine starts the application. It includes application, |
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4 | * board, and monitor specific initialization and configuration. |
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5 | * The generic CPU dependent initialization has been performed |
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6 | * before this routine is invoked. |
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7 | * |
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8 | * Copyright (c) 2006 by Atos Automacao Industrial Ltda. |
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9 | * written by Alain Schaefer <alain.schaefer@easc.ch> |
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10 | * and Antonio Giovanini <antonio@atos.com.br> |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.com/license/LICENSE. |
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15 | * |
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16 | * $Id$ |
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17 | */ |
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18 | |
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19 | |
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20 | #include <bsp.h> |
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21 | #include <libcpu/bf537.h> |
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22 | #include <libcpu/ebiuRegs.h> |
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23 | #include <libcpu/gpioRegs.h> |
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24 | #include <libcpu/mmu.h> |
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25 | #include <libcpu/mmuRegs.h> |
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26 | #include <libcpu/interrupt.h> |
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27 | |
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28 | |
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29 | static bfin_mmu_config_t mmuRegions = { |
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30 | /* instruction */ |
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31 | { |
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32 | {(void *) 0x00000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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33 | {(void *) 0x00400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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34 | {(void *) 0x00800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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35 | {(void *) 0x00c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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36 | {(void *) 0x01000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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37 | {(void *) 0x01400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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38 | {(void *) 0x01800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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39 | {(void *) 0x01c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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40 | {(void *) 0x02000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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41 | {(void *) 0x02400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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42 | {(void *) 0x02800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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43 | {(void *) 0x02c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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44 | {(void *) 0x03000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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45 | {(void *) 0x20000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, |
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46 | {(void *) 0xff800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE}, |
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47 | {(void *) 0xffc00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE} |
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48 | }, |
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49 | /* data */ |
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50 | { |
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51 | {(void *) 0x00000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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52 | {(void *) 0x00400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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53 | {(void *) 0x00800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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54 | {(void *) 0x00c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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55 | {(void *) 0x01000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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56 | {(void *) 0x01400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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57 | {(void *) 0x01800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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58 | {(void *) 0x01c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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59 | {(void *) 0x02000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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60 | {(void *) 0x02400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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61 | {(void *) 0x02800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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62 | {(void *) 0x02c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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63 | {(void *) 0x03000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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64 | {(void *) 0x20000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, |
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65 | {(void *) 0xff800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE}, |
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66 | {(void *) 0xffc00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE} |
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67 | } |
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68 | }; |
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69 | |
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70 | void Init_RTC(void); |
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71 | |
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72 | static void initPLL(void); |
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73 | static void initEBIU(void); |
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74 | static void initGPIO(void); |
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75 | |
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76 | /* |
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77 | * BSP pretasking hook. |
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78 | */ |
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79 | void bsp_pretasking_hook(void) |
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80 | { |
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81 | bfin_interrupt_init(); |
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82 | } |
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83 | |
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84 | /* |
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85 | * bsp_start |
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86 | * |
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87 | * This routine does the bulk of the BSP initialization. |
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88 | */ |
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89 | void bsp_start(void) |
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90 | { |
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91 | /* BSP Hardware Initialization*/ |
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92 | |
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93 | *(uint32_t volatile *) DMEM_CONTROL |= DMEM_CONTROL_PORT_PREF0; |
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94 | *(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_PORT_PREF1; |
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95 | bfin_mmu_init(&mmuRegions); |
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96 | rtems_cache_enable_instruction(); |
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97 | rtems_cache_enable_data(); |
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98 | |
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99 | Init_RTC(); /* Blackfin Real Time Clock initialization */ |
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100 | |
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101 | initPLL(); /* PLL initialization */ |
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102 | initEBIU(); /* EBIU initialization */ |
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103 | initGPIO(); /* GPIO initialization */ |
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104 | } |
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105 | |
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106 | /* |
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107 | * initPLL |
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108 | * |
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109 | * Routine to initialize the PLL. The BF537 Stamp uses a 27 Mhz XTAL. BISON |
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110 | * See "../bf537Stamp/include/bsp.h" for more information. |
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111 | */ |
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112 | |
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113 | static void initPLL(void) { |
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114 | |
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115 | #ifdef BISON |
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116 | unsigned int n; |
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117 | |
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118 | /* Configure PLL registers */ |
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119 | *((uint16_t*)PLL_LOCKCNT) = 0x1000; |
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120 | *((uint16_t*)PLL_DIV) = PLL_CSEL|PLL_SSEL; |
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121 | *((uint16_t*)PLL_CTL) = PLL_MSEL|PLL_DF; |
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122 | |
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123 | /* Commands to set PLL values */ |
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124 | asm("cli r0;"); |
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125 | asm("idle;"); |
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126 | asm("sti r0;"); |
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127 | |
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128 | /* Delay for PLL stabilization */ |
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129 | for (n=0; n<200; n++) {} |
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130 | #endif |
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131 | |
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132 | } |
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133 | |
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134 | /* |
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135 | * initEBIU |
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136 | * |
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137 | * Configure extern memory |
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138 | */ |
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139 | |
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140 | static void initEBIU(void) { |
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141 | |
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142 | /* by default the processor has priority over dma channels for access to |
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143 | external memory. this has been seen to result in dma unerruns on |
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144 | ethernet transmit; it seems likely it could cause dma overruns on |
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145 | ethernet receive as well. setting the following bit gives the dma |
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146 | channels priority over the cpu, fixing that problem. unfortunately |
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147 | we don't have finer grain control than that; all dma channels now |
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148 | have priority over the cpu. */ |
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149 | *(uint16_t volatile *) EBIU_AMGCTL |= EBIU_AMGCTL_CDPRIO; |
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150 | |
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151 | #ifdef BISON |
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152 | /* Configure FLASH */ |
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153 | *((uint32_t*)EBIU_AMBCTL0) = 0x7bb07bb0L; |
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154 | *((uint32_t*)EBIU_AMBCTL1) = 0x7bb07bb0L; |
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155 | *((uint16_t*)EBIU_AMGCTL) = 0x000f; |
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156 | |
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157 | /* Configure SDRAM |
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158 | *((uint32_t*)EBIU_SDGCTL) = 0x0091998d; |
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159 | *((uint16_t*)EBIU_SDBCTL) = 0x0013; |
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160 | *((uint16_t*)EBIU_SDRRC) = 0x0817; |
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161 | */ |
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162 | #endif |
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163 | } |
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164 | |
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165 | /* |
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166 | * initGPIO |
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167 | * |
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168 | * Enable LEDs port |
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169 | */ |
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170 | static void initGPIO(void) { |
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171 | #if (!BFIN_ON_SKYEYE) |
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172 | *(uint16_t volatile *) PORT_MUX = 0; |
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173 | |
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174 | /* port f bits 0, 1: uart0 tx, rx */ |
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175 | /* bits 2 - 5: buttons */ |
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176 | /* bits 6 - 11: leds */ |
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177 | *(uint16_t volatile *) PORTF_FER = 0x0003; |
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178 | *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000; |
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179 | *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x003c; |
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180 | *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000; |
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181 | *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000; |
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182 | *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000; |
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183 | *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000; |
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184 | *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000; |
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185 | *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0fc0; |
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186 | |
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187 | *(uint16_t volatile *) PORTG_FER = 0x0000; |
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188 | *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000; |
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189 | *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x0000; |
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190 | *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000; |
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191 | *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000; |
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192 | *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000; |
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193 | *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000; |
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194 | *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000; |
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195 | *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0000; |
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196 | |
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197 | /* port h bits 0 - 15: ethernet */ |
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198 | *(uint16_t volatile *) PORTH_FER = 0xffff; |
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199 | *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000; |
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200 | *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x0000; |
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201 | *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000; |
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202 | *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000; |
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203 | *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000; |
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204 | *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000; |
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205 | *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000; |
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206 | *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0000; |
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207 | #endif |
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208 | } |
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209 | |
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210 | /* |
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211 | * Helper Function to use the EzKits LEDS. |
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212 | * Can be used by the Application. |
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213 | */ |
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214 | void setLEDs(uint8_t value) { |
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215 | |
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216 | *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_CLEAR_OFFSET) = |
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217 | (uint16_t) (~value & 0x3f) << 6; |
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218 | *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_SET_OFFSET) = |
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219 | (uint16_t) (value & 0x3f) << 6; |
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220 | } |
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221 | |
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222 | /* |
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223 | * Helper Function to use the EzKits LEDS |
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224 | */ |
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225 | uint8_t getLEDs(void) { |
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226 | uint16_t r; |
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227 | |
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228 | r = *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET); |
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229 | return (uint8_t) ((r >> 6) & 0x3f); |
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230 | } |
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231 | |
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232 | uint8_t getButtons(void) { |
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233 | uint16_t r; |
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234 | |
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235 | r = *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET); |
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236 | |
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237 | return (uint8_t) ((r >> 2) & 0x0f); |
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238 | } |
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239 | |
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240 | |
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