1 | /* bspstart.c for TLL6527M |
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2 | * |
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3 | * This routine does the bulk of the system initialization. |
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4 | */ |
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5 | |
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6 | /* |
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7 | * COPYRIGHT (c) 2010 by ECE Northeastern University. |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.rtems.org/license |
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12 | */ |
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13 | |
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14 | #include <bsp.h> |
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15 | #include <bsp/bootcard.h> |
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16 | #include <cplb.h> |
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17 | #include <bsp/interrupt.h> |
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18 | #include <libcpu/ebiuRegs.h> |
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19 | |
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20 | const unsigned int dcplbs_table[16][2] = { |
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21 | { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, |
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22 | { 0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data B */ |
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23 | { 0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data A */ |
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24 | { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, |
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25 | |
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26 | { 0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 3 */ |
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27 | { 0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 2 */ |
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28 | { 0x20100000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 1 */ |
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29 | { 0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 0 */ |
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30 | |
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31 | { 0x02400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, |
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32 | { 0x02000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, |
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33 | { 0x00C00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, |
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34 | { 0x00800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, |
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35 | { 0x00400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, |
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36 | { 0x00000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, |
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37 | |
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38 | { 0xffffffff, 0xffffffff }/* end of section - termination */ |
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39 | }; |
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40 | |
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41 | |
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42 | const unsigned int _icplbs_table[16][2] = { |
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43 | { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) }, |
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44 | /* L1 Code */ |
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45 | { 0xEF000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* AREA DE BOOT */ |
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46 | { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, |
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47 | |
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48 | { 0x20300000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Memory Bank 3 */ |
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49 | { 0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 2 (Secnd) */ |
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50 | { 0x20100000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 1 (Prim B) */ |
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51 | { 0x20000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 0 (Prim A) */ |
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52 | |
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53 | { 0x02400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, |
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54 | { 0x02000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, |
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55 | { 0x00C00000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, |
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56 | { 0x00800000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, |
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57 | { 0x00400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, |
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58 | { 0x00000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, |
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59 | |
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60 | { 0xffffffff, 0xffffffff }/* end of section - termination */ |
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61 | }; |
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62 | |
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63 | /* |
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64 | * Init_PLL |
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65 | * |
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66 | * Routine to initialize the PLL. The TLL6527M uses a 25 Mhz XTAL. |
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67 | */ |
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68 | static void Init_PLL (void) |
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69 | { |
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70 | unsigned short msel = 0; |
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71 | unsigned short ssel = 0; |
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72 | |
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73 | msel = (unsigned short)( (float)CCLK/(float)CLKIN ); |
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74 | ssel = (unsigned short)( (float)(CLKIN*msel)/(float)SCLK); |
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75 | |
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76 | asm("cli r0;"); |
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77 | |
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78 | *((uint32_t*)SIC_IWR) = 0x1; |
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79 | |
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80 | /* Configure PLL registers */ |
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81 | *((uint16_t*)PLL_DIV) = ssel; |
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82 | msel = msel<<9; |
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83 | *((uint16_t*)PLL_CTL) = msel; |
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84 | |
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85 | /* Commands to set PLL values */ |
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86 | asm("idle;"); |
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87 | asm("sti r0;"); |
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88 | } |
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89 | |
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90 | /* |
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91 | * Init_EBIU |
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92 | * |
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93 | * Configure extern memory |
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94 | */ |
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95 | static void Init_EBIU (void) |
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96 | { |
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97 | /* Check if SDRAM is already enabled */ |
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98 | if ( 0 != (*(uint16_t *)EBIU_SDSTAT & EBIU_SDSTAT_SDRS) ){ |
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99 | asm("ssync;"); |
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100 | /* RDIV = (100MHz*64ms)/8192-(6+3)=0x406 cycles */ |
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101 | *(uint16_t *)EBIU_SDRRC = 0x3F6; /* SHould have been 0x306*/ |
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102 | *(uint16_t *)EBIU_SDBCTL = EBIU_SDBCTL_EBCAW_10 | EBIU_SDBCTL_EBSZ_64M | |
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103 | EBIU_SDBCTL_EBE; |
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104 | *(uint32_t *)EBIU_SDGCTL = 0x8491998d; |
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105 | asm("ssync;"); |
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106 | } else { |
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107 | /* SDRAm is already programmed */ |
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108 | } |
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109 | } |
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110 | |
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111 | /* |
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112 | * Init_Flags |
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113 | * |
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114 | * Enable LEDs port |
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115 | */ |
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116 | static void Init_Flags(void) |
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117 | { |
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118 | *((uint16_t*)PORTH_FER) = 0x0; |
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119 | *((uint16_t*)PORTH_MUX) = 0x0; |
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120 | *((uint16_t*)PORTHIO_DIR) = 0x1<<15; |
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121 | *((uint16_t*)PORTHIO_SET) = 0x1<<15; |
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122 | } |
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123 | |
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124 | /* |
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125 | * bsp_predriver_hook |
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126 | */ |
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127 | void bsp_predriver_hook(void) |
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128 | { |
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129 | bfin_interrupt_init(); |
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130 | } |
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131 | |
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132 | void bsp_start( void ) |
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133 | { |
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134 | int i; |
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135 | |
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136 | /* BSP Hardware Initialization*/ |
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137 | Init_RTC(); /* Blackfin Real Time Clock initialization */ |
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138 | Init_PLL(); /* PLL initialization */ |
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139 | Init_EBIU(); /* EBIU initialization */ |
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140 | Init_Flags(); /* GPIO initialization */ |
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141 | |
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142 | /* |
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143 | * Allocate the memory for the RTEMS Work Space. This can come from |
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144 | * a variety of places: hard coded address, malloc'ed from outside |
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145 | * RTEMS world (e.g. simulator or primitive memory manager), or (as |
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146 | * typically done by stock BSPs) by subtracting the required amount |
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147 | * of work space from the last physical address on the CPU board. |
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148 | */ |
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149 | for (i=5;i<16;i++) { |
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150 | set_vector((rtems_isr_entry)bfin_null_isr, i, 1); |
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151 | } |
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152 | |
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153 | } |
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