source: rtems/c/src/lib/libbsp/bfin/TLL6527M/startup/bspstart.c @ 721fe34

4.11
Last change on this file since 721fe34 was 721fe34, checked in by Joel Sherrill <joel.sherrill@…>, on May 31, 2012 at 8:34:36 PM

Fix C files which had two semi-colons at EOL

  • Property mode set to 100644
File size: 5.5 KB
Line 
1/*  bspstart.c for TLL6527M
2 *
3 *  This routine starts the application.  It includes application,
4 *  board, and monitor specific initialization and configuration.
5 *  The generic CPU dependent initialization has been performed
6 *  before this routine is invoked.
7 * 
8 * COPYRIGHT (c) 2010 by ECE Northeastern University.
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license
13 */
14
15
16#include <bsp.h>
17#include <cplb.h>
18#include <bsp/interrupt.h>
19#include <libcpu/ebiuRegs.h>
20
21const unsigned int dcplbs_table[16][2] = { 
22  { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },
23  { 0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data B */
24  { 0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data A */
25  { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },
26
27  { 0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 3 */
28  { 0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 2  */
29  { 0x20100000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 1 */
30  { 0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 0 */
31
32  { 0x02400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
33  { 0x02000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
34  { 0x00C00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
35  { 0x00800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
36  { 0x00400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
37  { 0x00000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
38
39  { 0xffffffff, 0xffffffff }/* end of section - termination */
40};
41
42
43const unsigned int _icplbs_table[16][2] = { 
44  { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) },
45  /* L1 Code */
46  { 0xEF000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* AREA DE BOOT */
47  { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },
48
49  { 0x20300000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Memory Bank 3 */
50  { 0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 2 (Secnd) */
51  { 0x20100000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 1 (Prim B) */
52  { 0x20000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 0 (Prim A) */
53
54  { 0x02400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
55  { 0x02000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
56  { 0x00C00000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
57  { 0x00800000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
58  { 0x00400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
59  { 0x00000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
60
61  { 0xffffffff, 0xffffffff }/* end of section - termination */
62};
63
64/*
65 *  Use the shared implementations of the following routines
66 */
67
68void bsp_libc_init( void *, uint32_t, int );
69void Init_PLL (void);
70void Init_EBIU (void);
71void Init_Flags(void);
72void Init_RTC (void);
73void initCPLB(void);
74
75
76void null_isr(void);
77
78/*
79 *  Function:   bsp_pretasking_hook
80 *  Created:    95/03/10
81 *
82 *  Description:
83 *      BSP pretasking hook.  Called just before drivers are initialized.
84 *      Used to setup libc and install any BSP extensions.
85 *
86 *  NOTES:
87 *      Must not use libc (to do io) from here, since drivers are
88 *      not yet initialized.
89 *
90 */
91
92void bsp_pretasking_hook(void)
93{
94  bfin_interrupt_init();
95}
96
97/*
98 *  bsp_start
99 *
100 *  This routine does the bulk of the system initialization.
101 */
102
103void bsp_start( void )
104{
105  /* BSP Hardware Initialization*/
106  Init_RTC();   /* Blackfin Real Time Clock initialization */ 
107  Init_PLL();   /* PLL initialization */
108  Init_EBIU();  /* EBIU initialization */
109  Init_Flags(); /* GPIO initialization */
110
111  /*
112   *  Allocate the memory for the RTEMS Work Space.  This can come from
113   *  a variety of places: hard coded address, malloc'ed from outside
114   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
115   *  typically done by stock BSPs) by subtracting the required amount
116   *  of work space from the last physical address on the CPU board.
117   */
118  int i=0;
119  for (i=5;i<16;i++) {
120    set_vector((rtems_isr_entry)null_isr, i, 1);
121  }
122 
123}
124
125 /*
126  * Init_PLL
127  *
128  * Routine to initialize the PLL. The TLL6527M uses a 25 Mhz XTAL.
129  */
130void Init_PLL (void)
131{
132  unsigned short msel = 0;
133  unsigned short ssel = 0;
134
135  msel = (unsigned short)( (float)CCLK/(float)CLKIN );
136  ssel = (unsigned short)( (float)(CLKIN*msel)/(float)SCLK);
137 
138  asm("cli r0;");
139
140  *((uint32_t*)SIC_IWR) = 0x1;
141
142  /* Configure PLL registers */
143  *((uint16_t*)PLL_DIV) = ssel;
144  msel = msel<<9;
145  *((uint16_t*)PLL_CTL) = msel;
146
147  /* Commands to set PLL values */
148  asm("idle;");
149  asm("sti r0;");
150}
151
152 /*
153  * Init_EBIU
154  *
155  * Configure extern memory
156  */
157
158void Init_EBIU (void)
159{
160  /* Check if SDRAM is already enabled */
161  if ( 0 != (*(uint16_t *)EBIU_SDSTAT & EBIU_SDSTAT_SDRS) ){
162    asm("ssync;");
163    /* RDIV = (100MHz*64ms)/8192-(6+3)=0x406 cycles */
164    *(uint16_t *)EBIU_SDRRC  = 0x3F6; /* SHould have been 0x306*/
165    *(uint16_t *)EBIU_SDBCTL = EBIU_SDBCTL_EBCAW_10 | EBIU_SDBCTL_EBSZ_64M |
166        EBIU_SDBCTL_EBE;
167    *(uint32_t *)EBIU_SDGCTL = 0x8491998d;
168    asm("ssync;");
169  } else {
170    /* SDRAm is already programmed */
171  }
172}
173
174 /*
175  * Init_Flags
176  *
177  * Enable LEDs port
178  */
179void Init_Flags(void)
180{
181  *((uint16_t*)PORTH_FER)    = 0x0;
182  *((uint16_t*)PORTH_MUX)    = 0x0;
183  *((uint16_t*)PORTHIO_DIR)  = 0x1<<15;
184  *((uint16_t*)PORTHIO_SET)  = 0x1<<15;
185}
186
187
188
189void initCPLB(void) {
190
191       int i = 0;
192       unsigned int *addr;
193       unsigned int *data;
194       
195       addr = (unsigned int *)0xffe00100;
196       data = (unsigned int *)0xffe00200;
197
198       while ( dcplbs_table[i][0] != 0xffffffff ) {
199               *addr = dcplbs_table[i][0];
200               *data = dcplbs_table[i][1];
201
202               addr++;
203               data++;
204       } 
205}
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