source: rtems/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h @ ad65fc7f

4.115
Last change on this file since ad65fc7f was ad65fc7f, checked in by Joel Sherrill <joel.sherrill@…>, on 04/20/11 at 20:23:39

2011-04-20 Rohan Kangralkar <rkangral@…>

PR 1781/bsps

  • ChangeLog?, Makefile.am, README, bsp_specs, configure.ac, preinstall.am, times, console/console.c, include/bsp.h, include/cplb.h, include/tm27.h, make/custom/TLL6527M.cfg, startup/bspstart.c, startup/linkcmds: New files. Initial port for the TLL6527Mboard that contains blackfin 52X range of processors. Used eZKit533 as a reference for building the port.
  • Property mode set to 100644
File size: 1.1 KB
Line 
1/*  cplb.h
2 * 
3 *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
4 *             written by Alain Schaefer <alain.schaefer@easc.ch>
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 *  $Id$
11 */
12#ifndef _CPLB_H
13#define _CPLB_H
14
15/* CPLB configurations */
16#define CPLB_DEF_CACHE_WT       CPLB_L1_CHBL | CPLB_WT
17#define CPLB_DEF_CACHE_WB       CPLB_L1_CHBL
18#define CPLB_CACHE_ENABLED      CPLB_L1_CHBL | CPLB_DIRTY
19
20#define CPLB_DEF_CACHE          CPLB_L1_CHBL | CPLB_WT
21#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
22
23#define CPLB_I_PAGE_MGMT        CPLB_LOCK | CPLB_VALID
24#define CPLB_D_PAGE_MGMT        CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
25
26#define CPLB_DNOCACHE           CPLB_ALL_ACCESS | CPLB_VALID
27#define CPLB_DDOCACHE           CPLB_DNOCACHE | CPLB_DEF_CACHE
28#define CPLB_INOCACHE           CPLB_USER_RD | CPLB_VALID
29#define CPLB_IDOCACHE           CPLB_INOCACHE | CPLB_L1_CHBL
30
31#define CPLB_DDOCACHE_WT        CPLB_DNOCACHE | CPLB_DEF_CACHE_WT
32#define CPLB_DDOCACHE_WB        CPLB_DNOCACHE | CPLB_DEF_CACHE_WB
33
34#endif /* _CPLB_H */
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