4.115
Last change
on this file since 183af89 was
ad65fc7f,
checked in by Joel Sherrill <joel.sherrill@…>, on 04/20/11 at 20:23:39
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2011-04-20 Rohan Kangralkar <rkangral@…>
PR 1781/bsps
- ChangeLog?, Makefile.am, README, bsp_specs, configure.ac,
preinstall.am, times, console/console.c, include/bsp.h,
include/cplb.h, include/tm27.h, make/custom/TLL6527M.cfg,
startup/bspstart.c, startup/linkcmds: New files.
Initial port for the TLL6527Mboard that contains blackfin 52X
range of processors. Used eZKit533 as a reference for building
the port.
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-
Property mode set to
100644
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File size:
1.1 KB
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1 | /* cplb.h |
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2 | * |
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3 | * Copyright (c) 2006 by Atos Automacao Industrial Ltda. |
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4 | * written by Alain Schaefer <alain.schaefer@easc.ch> |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.com/license/LICENSE. |
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9 | * |
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10 | * $Id$ |
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11 | */ |
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12 | #ifndef _CPLB_H |
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13 | #define _CPLB_H |
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14 | |
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15 | /* CPLB configurations */ |
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16 | #define CPLB_DEF_CACHE_WT CPLB_L1_CHBL | CPLB_WT |
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17 | #define CPLB_DEF_CACHE_WB CPLB_L1_CHBL |
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18 | #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY |
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19 | |
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20 | #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT |
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21 | #define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR |
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22 | |
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23 | #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID |
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24 | #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID |
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25 | |
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26 | #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID |
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27 | #define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE |
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28 | #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID |
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29 | #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL |
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30 | |
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31 | #define CPLB_DDOCACHE_WT CPLB_DNOCACHE | CPLB_DEF_CACHE_WT |
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32 | #define CPLB_DDOCACHE_WB CPLB_DNOCACHE | CPLB_DEF_CACHE_WB |
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33 | |
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34 | #endif /* _CPLB_H */ |
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