source: rtems/c/src/lib/libbsp/arm/xilinx-zynqmp/configure.ac @ 77f9a1b

5
Last change on this file since 77f9a1b was 77f9a1b, checked in by Jeff Kubascik <jeff.kubascik@…>, on 04/10/19 at 23:38:55

bsp/xilinx-zynqmp: Implement Ultra96 target

Modifications to get xilinx-zynqmp BSP working on an Ultra96 board.

Update #3682.

  • Property mode set to 100644
File size: 4.7 KB
Line 
1##
2#
3# @file
4#
5# @brief Configure script of LibBSP for the Xilinx Zynq UltraScale+ MPSoC platform.
6#
7
8AC_PREREQ([2.69])
9AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynqmp-a53],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
10RTEMS_TOP(../../../../../..)
11RTEMS_SOURCE_TOP
12RTEMS_BUILD_TOP
13
14RTEMS_CANONICAL_TARGET_CPU
15AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
16RTEMS_BSP_CONFIGURE
17
18
19
20RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
21RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
22
23RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*qemu],[])
24RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1])
25RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache])
26
27RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*qemu],[])
28RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1])
29RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache])
30
31RTEMS_BSPOPTS_SET([ARM_GENERIC_TIMER_USE_VIRTUAL],[*],[])
32RTEMS_BSPOPTS_HELP([ARM_GENERIC_TIMER_USE_VIRTUAL],[Use virtual ARM generic timer])
33
34RTEMS_BSPOPTS_SET([ARM_GENERIC_TIMER_FREQ],[*],[])
35RTEMS_BSPOPTS_HELP([ARM_GENERIC_TIMER_FREQ],[ARM generic timer frequency in Hz])
36
37RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynqmp_ultra96*],[100000000UL])
38RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[*],[100000000UL])
39RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_UART],[Zynq UART clock frequency in Hz])
40
41USE_FAST_IDLE=0
42AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynqmp_a53_qemu], [USE_FAST_IDLE=1])
43
44RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[${USE_FAST_IDLE}])
45RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_FAST_IDLE],
46[This sets a mode where the time runs as fast as possible when a clock ISR
47occurs while the IDLE thread is executing.  This can significantly reduce
48simulation times.])
49
50RTEMS_BSPOPTS_SET([BSP_CONSOLE_MINOR],[*],[1])
51RTEMS_BSPOPTS_HELP([BSP_CONSOLE_MINOR],[minor number of console device])
52
53RTEMS_BSPOPTS_SET([ZYNQ_CONSOLE_USE_INTERRUPTS],[*],[1])
54RTEMS_BSPOPTS_HELP([ZYNQ_CONSOLE_USE_INTERRUPTS],[use interrupt driven mode for console devices (used by default)])
55
56#
57# Zynq Memory map can be controlled from the configure command line. Use ...
58#
59#   ..../configure --target=arm-rtems4.11 ... BSP_ZYNQMP_RAM_LENGTH=256M
60#
61RTEMS_BSPOPTS_SET([BSP_ZYNQMP_RAM_LENGTH],[xilinx_zynqmp_ultra96],[2048M])
62RTEMS_BSPOPTS_SET([BSP_ZYNQMP_RAM_LENGTH],[*],[256M])
63RTEMS_BSPOPTS_HELP([BSP_ZYNQMP_RAM_LENGTH],[override a BSP's default RAM length])
64
65RTEMS_BSPOPTS_SET([BSP_ZYNQMP_NOCACHE_LENGTH],[*],[1M])
66RTEMS_BSPOPTS_HELP([BSP_ZYNQMP_NOCACHE_LENGTH],[length of nocache RAM region])
67
68AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynqmp_a53_qemu],
69      [ZYNQMP_RAM_ORIGIN="0x00000000"
70       ZYNQMP_RAM_MMU="0x0fffc000"
71       ZYNQMP_RAM_MMU_LENGTH="16k"
72       ZYNQMP_RAM_ORIGIN_AVAILABLE="${ZYNQMP_RAM_ORIGIN}"
73       ZYNQMP_RAM_LENGTH_AVAILABLE="${BSP_ZYNQMP_RAM_LENGTH} - 16k"
74       ZYNQMP_RAM_INT_0_ORIGIN="0x00000000"
75       ZYNQMP_RAM_INT_0_LENGTH="64k + 64k + 64k"
76       ZYNQMP_RAM_INT_1_ORIGIN="0xFFFF0000"
77       ZYNQMP_RAM_INT_1_LENGTH="64k - 512"])
78
79AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynqmp_ultra96],
80      [ZYNQMP_RAM_ORIGIN="0x00100000"
81       ZYNQMP_RAM_MMU="${ZYNQMP_RAM_ORIGIN}"
82       ZYNQMP_RAM_MMU_LENGTH="16k"
83       ZYNQMP_RAM_ORIGIN_AVAILABLE="${ZYNQMP_RAM_ORIGIN} + 0x00004000"
84       ZYNQMP_RAM_LENGTH_AVAILABLE="${BSP_ZYNQMP_RAM_LENGTH} - 1M - 16k"
85       ZYNQMP_RAM_INT_0_ORIGIN="0x00000000"
86       ZYNQMP_RAM_INT_0_LENGTH="64k + 64k + 64k"
87       ZYNQMP_RAM_INT_1_ORIGIN="0xFFFF0000"
88       ZYNQMP_RAM_INT_1_LENGTH="64k - 512"])
89
90AC_DEFUN([ZYNQMP_LINKCMD],[
91AC_ARG_VAR([$1],[$2; default $3])dnl
92[$1]=[$]{[$1]:-[$3]}
93])
94
95ZYNQMP_LINKCMD([ZYNQMP_RAM_ORIGIN],[normal RAM region origin],[${ZYNQMP_RAM_ORIGIN}])
96ZYNQMP_LINKCMD([ZYNQMP_RAM_LENGTH],[normal RAM region length],[${BSP_ZYNQMP_RAM_LENGTH}])
97ZYNQMP_LINKCMD([ZYNQMP_RAM_MMU],[MMU region origin],[${ZYNQMP_RAM_MMU}])
98ZYNQMP_LINKCMD([ZYNQMP_RAM_MMU_LENGTH],[MMU region length],[${ZYNQMP_RAM_MMU_LENGTH}])
99ZYNQMP_LINKCMD([ZYNQMP_RAM_ORIGIN_AVAILABLE],[origin of available RAM],[${ZYNQMP_RAM_ORIGIN_AVAILABLE}])
100ZYNQMP_LINKCMD([ZYNQMP_RAM_LENGTH_AVAILABLE],[length of available RAM],[${ZYNQMP_RAM_LENGTH_AVAILABLE}])
101ZYNQMP_LINKCMD([ZYNQMP_RAM_NOCACHE_LENGTH],[length of nocache RAM region],[${BSP_ZYNQMP_NOCACHE_LENGTH}])
102ZYNQMP_LINKCMD([ZYNQMP_RAM_INT_0_ORIGIN],[internal 0 RAM region origin],[${ZYNQMP_RAM_INT_0_ORIGIN}])
103ZYNQMP_LINKCMD([ZYNQMP_RAM_INT_0_LENGTH],[internal 0 RAM region length],[${ZYNQMP_RAM_INT_0_LENGTH}])
104ZYNQMP_LINKCMD([ZYNQMP_RAM_INT_1_ORIGIN],[internal 1 RAM region origin],[${ZYNQMP_RAM_INT_1_ORIGIN}])
105ZYNQMP_LINKCMD([ZYNQMP_RAM_INT_1_LENGTH],[internal 1 RAM region length],[${ZYNQMP_RAM_INT_1_LENGTH}])
106
107RTEMS_BSP_CLEANUP_OPTIONS
108
109AC_CONFIG_FILES([
110Makefile
111linkcmds:../../../../../../bsps/arm/xilinx-zynqmp/start/linkcmds.in])
112AC_OUTPUT
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