4.115
Last change
on this file since 50440c0 was
50440c0,
checked in by Sebastian Huber <sebastian.huber@…>, on 11/19/14 at 14:30:24
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bsps/arm: Enable L2C for Cortex-A9 MPCore BSPs
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Property mode set to
100644
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File size:
948 bytes
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1 | /* |
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2 | * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION |
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16 | |
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17 | #include <bsp.h> |
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18 | #include <bsp/start.h> |
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19 | #include <bsp/arm-cp15-start.h> |
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20 | #include <bsp/arm-a9mpcore-start.h> |
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21 | |
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22 | BSP_START_TEXT_SECTION void bsp_start_hook_0(void) |
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23 | { |
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24 | arm_a9mpcore_start_hook_0(); |
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25 | } |
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26 | |
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27 | BSP_START_TEXT_SECTION void bsp_start_hook_1(void) |
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28 | { |
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29 | arm_a9mpcore_start_hook_1(); |
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30 | bsp_start_copy_sections(); |
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31 | zynq_setup_mmu_and_cache(); |
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32 | |
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33 | #if !defined(RTEMS_SMP) \ |
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34 | && (defined(BSP_DATA_CACHE_ENABLED) \ |
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35 | || defined(BSP_INSTRUCTION_CACHE_ENABLED)) |
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36 | /* Enable unified L2 cache */ |
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37 | rtems_cache_enable_data(); |
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38 | #endif |
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39 | |
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40 | bsp_start_clear_bss(); |
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41 | } |
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