source: rtems/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c @ 50440c0

4.115
Last change on this file since 50440c0 was 50440c0, checked in by Sebastian Huber <sebastian.huber@…>, on 11/19/14 at 14:30:24

bsps/arm: Enable L2C for Cortex-A9 MPCore BSPs

  • Property mode set to 100644
File size: 948 bytes
Line 
1/*
2 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION
16
17#include <bsp.h>
18#include <bsp/start.h>
19#include <bsp/arm-cp15-start.h>
20#include <bsp/arm-a9mpcore-start.h>
21
22BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
23{
24  arm_a9mpcore_start_hook_0();
25}
26
27BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
28{
29  arm_a9mpcore_start_hook_1();
30  bsp_start_copy_sections();
31  zynq_setup_mmu_and_cache();
32
33#if !defined(RTEMS_SMP) \
34  && (defined(BSP_DATA_CACHE_ENABLED) \
35    || defined(BSP_INSTRUCTION_CACHE_ENABLED))
36  /* Enable unified L2 cache */
37  rtems_cache_enable_data();
38#endif
39
40  bsp_start_clear_bss();
41}
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