source: rtems/c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-uart-regs.h @ a94d46c8

4.115
Last change on this file since a94d46c8 was a94d46c8, checked in by Sebastian Huber <sebastian.huber@…>, on May 6, 2013 at 12:34:55 PM

bsp/xilinx-zynq: New BSP

  • Property mode set to 100644
File size: 5.6 KB
Line 
1/*
2 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
16#define LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
17
18#include <bsp/utility.h>
19
20typedef struct {
21        uint32_t control;
22#define ZYNQ_UART_CONTROL_STPBRK BSP_BIT32(8)
23#define ZYNQ_UART_CONTROL_STTBRK BSP_BIT32(7)
24#define ZYNQ_UART_CONTROL_RSTTO BSP_BIT32(6)
25#define ZYNQ_UART_CONTROL_TXDIS BSP_BIT32(5)
26#define ZYNQ_UART_CONTROL_TXEN BSP_BIT32(4)
27#define ZYNQ_UART_CONTROL_RXDIS BSP_BIT32(3)
28#define ZYNQ_UART_CONTROL_RXEN BSP_BIT32(2)
29#define ZYNQ_UART_CONTROL_TXRES BSP_BIT32(1)
30#define ZYNQ_UART_CONTROL_RXRES BSP_BIT32(0)
31        uint32_t mode;
32#define ZYNQ_UART_MODE_CHMODE(val) BSP_FLD32(val, 8, 9)
33#define ZYNQ_UART_MODE_CHMODE_GET(reg) BSP_FLD32GET(reg, 8, 9)
34#define ZYNQ_UART_MODE_CHMODE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
35#define ZYNQ_UART_MODE_CHMODE_NORMAL 0x00U
36#define ZYNQ_UART_MODE_CHMODE_AUTO_ECHO 0x01U
37#define ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK 0x02U
38#define ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK 0x03U
39#define ZYNQ_UART_MODE_NBSTOP(val) BSP_FLD32(val, 6, 7)
40#define ZYNQ_UART_MODE_NBSTOP_GET(reg) BSP_FLD32GET(reg, 6, 7)
41#define ZYNQ_UART_MODE_NBSTOP_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7)
42#define ZYNQ_UART_MODE_NBSTOP_STOP_1 0x00U
43#define ZYNQ_UART_MODE_NBSTOP_STOP_1_5 0x01U
44#define ZYNQ_UART_MODE_NBSTOP_STOP_2 0x02U
45#define ZYNQ_UART_MODE_PAR(val) BSP_FLD32(val, 3, 5)
46#define ZYNQ_UART_MODE_PAR_GET(reg) BSP_FLD32GET(reg, 3, 5)
47#define ZYNQ_UART_MODE_PAR_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
48#define ZYNQ_UART_MODE_PAR_EVEN 0x00U
49#define ZYNQ_UART_MODE_PAR_ODD 0x01U
50#define ZYNQ_UART_MODE_PAR_SPACE 0x02U
51#define ZYNQ_UART_MODE_PAR_MARK 0x03U
52#define ZYNQ_UART_MODE_PAR_NONE 0x04U
53#define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2)
54#define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2)
55#define ZYNQ_UART_MODE_CHRL_SET(reg, val) BSP_FLD32SET(reg, val, 1, 2)
56#define ZYNQ_UART_MODE_CHRL_8 0x00U
57#define ZYNQ_UART_MODE_CHRL_7 0x02U
58#define ZYNQ_UART_MODE_CHRL_6 0x03U
59#define ZYNQ_UART_MODE_CLKS BSP_BIT32(0)
60        uint32_t irq_en;
61        uint32_t irq_dis;
62        uint32_t irq_mask;
63        uint32_t irq_sts;
64#define ZYNQ_UART_TOVR BSP_BIT32(12)
65#define ZYNQ_UART_TNFUL BSP_BIT32(11)
66#define ZYNQ_UART_TTRIG BSP_BIT32(10)
67#define ZYNQ_UART_DMSI BSP_BIT32(9)
68#define ZYNQ_UART_TIMEOUT BSP_BIT32(8)
69#define ZYNQ_UART_PARE BSP_BIT32(7)
70#define ZYNQ_UART_FRAME BSP_BIT32(6)
71#define ZYNQ_UART_ROVR BSP_BIT32(5)
72#define ZYNQ_UART_TFUL BSP_BIT32(4)
73#define ZYNQ_UART_TEMPTY BSP_BIT32(3)
74#define ZYNQ_UART_RFUL BSP_BIT32(2)
75#define ZYNQ_UART_REMPTY BSP_BIT32(1)
76#define ZYNQ_UART_RTRIG BSP_BIT32(0)
77        uint32_t baud_rate_gen;
78#define ZYNQ_UART_BAUD_RATE_GEN_CD(val) BSP_FLD32(val, 0, 15)
79#define ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg) BSP_FLD32GET(reg, 0, 15)
80#define ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
81        uint32_t rx_timeout;
82#define ZYNQ_UART_RX_TIMEOUT_RTO(val) BSP_FLD32(val, 0, 7)
83#define ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg) BSP_FLD32GET(reg, 0, 7)
84#define ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
85        uint32_t rx_fifo_trg_lvl;
86#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val) BSP_FLD32(val, 0, 5)
87#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
88#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
89        uint32_t modem_ctrl;
90#define ZYNQ_UART_MODEM_CTRL_FCM BSP_BIT32(5)
91#define ZYNQ_UART_MODEM_CTRL_RTS BSP_BIT32(1)
92#define ZYNQ_UART_MODEM_CTRL_DTR BSP_BIT32(0)
93        uint32_t modem_sts;
94#define ZYNQ_UART_MODEM_STS_FCMS BSP_BIT32(8)
95#define ZYNQ_UART_MODEM_STS_DCD BSP_BIT32(7)
96#define ZYNQ_UART_MODEM_STS_RI BSP_BIT32(6)
97#define ZYNQ_UART_MODEM_STS_DSR BSP_BIT32(5)
98#define ZYNQ_UART_MODEM_STS_CTS BSP_BIT32(4)
99#define ZYNQ_UART_MODEM_STS_DDCD BSP_BIT32(3)
100#define ZYNQ_UART_MODEM_STS_TERI BSP_BIT32(2)
101#define ZYNQ_UART_MODEM_STS_DDSR BSP_BIT32(1)
102#define ZYNQ_UART_MODEM_STS_DCTS BSP_BIT32(0)
103        uint32_t channel_sts;
104#define ZYNQ_UART_CHANNEL_STS_TNFUL BSP_BIT32(14)
105#define ZYNQ_UART_CHANNEL_STS_TTRIG BSP_BIT32(13)
106#define ZYNQ_UART_CHANNEL_STS_FDELT BSP_BIT32(12)
107#define ZYNQ_UART_CHANNEL_STS_TACTIVE BSP_BIT32(11)
108#define ZYNQ_UART_CHANNEL_STS_RACTIVE BSP_BIT32(10)
109#define ZYNQ_UART_CHANNEL_STS_TFUL BSP_BIT32(4)
110#define ZYNQ_UART_CHANNEL_STS_TEMPTY BSP_BIT32(3)
111#define ZYNQ_UART_CHANNEL_STS_RFUL BSP_BIT32(2)
112#define ZYNQ_UART_CHANNEL_STS_REMPTY BSP_BIT32(1)
113#define ZYNQ_UART_CHANNEL_STS_RTRIG BSP_BIT32(0)
114        uint32_t tx_rx_fifo;
115#define ZYNQ_UART_TX_RX_FIFO_FIFO(val) BSP_FLD32(val, 0, 7)
116#define ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg) BSP_FLD32GET(reg, 0, 7)
117#define ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
118        uint32_t baud_rate_div;
119#define ZYNQ_UART_BAUD_RATE_DIV_BDIV(val) BSP_FLD32(val, 0, 7)
120#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg) BSP_FLD32GET(reg, 0, 7)
121#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
122        uint32_t flow_delay;
123#define ZYNQ_UART_FLOW_DELAY_FDEL(val) BSP_FLD32(val, 0, 5)
124#define ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg) BSP_FLD32GET(reg, 0, 5)
125#define ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
126        uint32_t reserved_3c[2];
127        uint32_t tx_fifo_trg_lvl;
128#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val) BSP_FLD32(val, 0, 5)
129#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
130#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
131} zynq_uart;
132
133#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */
Note: See TracBrowser for help on using the repository browser.