[a94d46c8] | 1 | /* |
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| 2 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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| 3 | * |
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| 4 | * embedded brains GmbH |
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| 5 | * Dornierstr. 4 |
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| 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <info@embedded-brains.de> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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| 12 | * http://www.rtems.com/license/LICENSE. |
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| 13 | */ |
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| 14 | |
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| 15 | #ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H |
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| 16 | #define LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H |
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| 17 | |
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| 18 | #include <bsp/utility.h> |
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| 19 | |
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| 20 | typedef struct { |
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| 21 | uint32_t control; |
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| 22 | #define ZYNQ_UART_CONTROL_STPBRK BSP_BIT32(8) |
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| 23 | #define ZYNQ_UART_CONTROL_STTBRK BSP_BIT32(7) |
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| 24 | #define ZYNQ_UART_CONTROL_RSTTO BSP_BIT32(6) |
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| 25 | #define ZYNQ_UART_CONTROL_TXDIS BSP_BIT32(5) |
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| 26 | #define ZYNQ_UART_CONTROL_TXEN BSP_BIT32(4) |
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| 27 | #define ZYNQ_UART_CONTROL_RXDIS BSP_BIT32(3) |
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| 28 | #define ZYNQ_UART_CONTROL_RXEN BSP_BIT32(2) |
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| 29 | #define ZYNQ_UART_CONTROL_TXRES BSP_BIT32(1) |
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| 30 | #define ZYNQ_UART_CONTROL_RXRES BSP_BIT32(0) |
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| 31 | uint32_t mode; |
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| 32 | #define ZYNQ_UART_MODE_CHMODE(val) BSP_FLD32(val, 8, 9) |
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| 33 | #define ZYNQ_UART_MODE_CHMODE_GET(reg) BSP_FLD32GET(reg, 8, 9) |
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| 34 | #define ZYNQ_UART_MODE_CHMODE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9) |
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| 35 | #define ZYNQ_UART_MODE_CHMODE_NORMAL 0x00U |
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| 36 | #define ZYNQ_UART_MODE_CHMODE_AUTO_ECHO 0x01U |
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| 37 | #define ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK 0x02U |
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| 38 | #define ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK 0x03U |
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| 39 | #define ZYNQ_UART_MODE_NBSTOP(val) BSP_FLD32(val, 6, 7) |
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| 40 | #define ZYNQ_UART_MODE_NBSTOP_GET(reg) BSP_FLD32GET(reg, 6, 7) |
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| 41 | #define ZYNQ_UART_MODE_NBSTOP_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7) |
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| 42 | #define ZYNQ_UART_MODE_NBSTOP_STOP_1 0x00U |
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| 43 | #define ZYNQ_UART_MODE_NBSTOP_STOP_1_5 0x01U |
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| 44 | #define ZYNQ_UART_MODE_NBSTOP_STOP_2 0x02U |
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| 45 | #define ZYNQ_UART_MODE_PAR(val) BSP_FLD32(val, 3, 5) |
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| 46 | #define ZYNQ_UART_MODE_PAR_GET(reg) BSP_FLD32GET(reg, 3, 5) |
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| 47 | #define ZYNQ_UART_MODE_PAR_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) |
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| 48 | #define ZYNQ_UART_MODE_PAR_EVEN 0x00U |
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| 49 | #define ZYNQ_UART_MODE_PAR_ODD 0x01U |
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| 50 | #define ZYNQ_UART_MODE_PAR_SPACE 0x02U |
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| 51 | #define ZYNQ_UART_MODE_PAR_MARK 0x03U |
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| 52 | #define ZYNQ_UART_MODE_PAR_NONE 0x04U |
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| 53 | #define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2) |
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| 54 | #define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2) |
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| 55 | #define ZYNQ_UART_MODE_CHRL_SET(reg, val) BSP_FLD32SET(reg, val, 1, 2) |
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| 56 | #define ZYNQ_UART_MODE_CHRL_8 0x00U |
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| 57 | #define ZYNQ_UART_MODE_CHRL_7 0x02U |
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| 58 | #define ZYNQ_UART_MODE_CHRL_6 0x03U |
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| 59 | #define ZYNQ_UART_MODE_CLKS BSP_BIT32(0) |
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| 60 | uint32_t irq_en; |
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| 61 | uint32_t irq_dis; |
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| 62 | uint32_t irq_mask; |
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| 63 | uint32_t irq_sts; |
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| 64 | #define ZYNQ_UART_TOVR BSP_BIT32(12) |
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| 65 | #define ZYNQ_UART_TNFUL BSP_BIT32(11) |
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| 66 | #define ZYNQ_UART_TTRIG BSP_BIT32(10) |
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| 67 | #define ZYNQ_UART_DMSI BSP_BIT32(9) |
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| 68 | #define ZYNQ_UART_TIMEOUT BSP_BIT32(8) |
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| 69 | #define ZYNQ_UART_PARE BSP_BIT32(7) |
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| 70 | #define ZYNQ_UART_FRAME BSP_BIT32(6) |
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| 71 | #define ZYNQ_UART_ROVR BSP_BIT32(5) |
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| 72 | #define ZYNQ_UART_TFUL BSP_BIT32(4) |
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| 73 | #define ZYNQ_UART_TEMPTY BSP_BIT32(3) |
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| 74 | #define ZYNQ_UART_RFUL BSP_BIT32(2) |
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| 75 | #define ZYNQ_UART_REMPTY BSP_BIT32(1) |
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| 76 | #define ZYNQ_UART_RTRIG BSP_BIT32(0) |
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| 77 | uint32_t baud_rate_gen; |
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| 78 | #define ZYNQ_UART_BAUD_RATE_GEN_CD(val) BSP_FLD32(val, 0, 15) |
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| 79 | #define ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg) BSP_FLD32GET(reg, 0, 15) |
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| 80 | #define ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) |
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| 81 | uint32_t rx_timeout; |
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| 82 | #define ZYNQ_UART_RX_TIMEOUT_RTO(val) BSP_FLD32(val, 0, 7) |
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| 83 | #define ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg) BSP_FLD32GET(reg, 0, 7) |
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| 84 | #define ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) |
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| 85 | uint32_t rx_fifo_trg_lvl; |
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| 86 | #define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val) BSP_FLD32(val, 0, 5) |
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| 87 | #define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5) |
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| 88 | #define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) |
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| 89 | uint32_t modem_ctrl; |
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| 90 | #define ZYNQ_UART_MODEM_CTRL_FCM BSP_BIT32(5) |
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| 91 | #define ZYNQ_UART_MODEM_CTRL_RTS BSP_BIT32(1) |
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| 92 | #define ZYNQ_UART_MODEM_CTRL_DTR BSP_BIT32(0) |
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| 93 | uint32_t modem_sts; |
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| 94 | #define ZYNQ_UART_MODEM_STS_FCMS BSP_BIT32(8) |
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| 95 | #define ZYNQ_UART_MODEM_STS_DCD BSP_BIT32(7) |
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| 96 | #define ZYNQ_UART_MODEM_STS_RI BSP_BIT32(6) |
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| 97 | #define ZYNQ_UART_MODEM_STS_DSR BSP_BIT32(5) |
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| 98 | #define ZYNQ_UART_MODEM_STS_CTS BSP_BIT32(4) |
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| 99 | #define ZYNQ_UART_MODEM_STS_DDCD BSP_BIT32(3) |
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| 100 | #define ZYNQ_UART_MODEM_STS_TERI BSP_BIT32(2) |
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| 101 | #define ZYNQ_UART_MODEM_STS_DDSR BSP_BIT32(1) |
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| 102 | #define ZYNQ_UART_MODEM_STS_DCTS BSP_BIT32(0) |
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| 103 | uint32_t channel_sts; |
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| 104 | #define ZYNQ_UART_CHANNEL_STS_TNFUL BSP_BIT32(14) |
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| 105 | #define ZYNQ_UART_CHANNEL_STS_TTRIG BSP_BIT32(13) |
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| 106 | #define ZYNQ_UART_CHANNEL_STS_FDELT BSP_BIT32(12) |
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| 107 | #define ZYNQ_UART_CHANNEL_STS_TACTIVE BSP_BIT32(11) |
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| 108 | #define ZYNQ_UART_CHANNEL_STS_RACTIVE BSP_BIT32(10) |
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| 109 | #define ZYNQ_UART_CHANNEL_STS_TFUL BSP_BIT32(4) |
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| 110 | #define ZYNQ_UART_CHANNEL_STS_TEMPTY BSP_BIT32(3) |
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| 111 | #define ZYNQ_UART_CHANNEL_STS_RFUL BSP_BIT32(2) |
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| 112 | #define ZYNQ_UART_CHANNEL_STS_REMPTY BSP_BIT32(1) |
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| 113 | #define ZYNQ_UART_CHANNEL_STS_RTRIG BSP_BIT32(0) |
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| 114 | uint32_t tx_rx_fifo; |
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| 115 | #define ZYNQ_UART_TX_RX_FIFO_FIFO(val) BSP_FLD32(val, 0, 7) |
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| 116 | #define ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg) BSP_FLD32GET(reg, 0, 7) |
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| 117 | #define ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) |
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| 118 | uint32_t baud_rate_div; |
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| 119 | #define ZYNQ_UART_BAUD_RATE_DIV_BDIV(val) BSP_FLD32(val, 0, 7) |
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| 120 | #define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg) BSP_FLD32GET(reg, 0, 7) |
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| 121 | #define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) |
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| 122 | uint32_t flow_delay; |
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| 123 | #define ZYNQ_UART_FLOW_DELAY_FDEL(val) BSP_FLD32(val, 0, 5) |
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| 124 | #define ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg) BSP_FLD32GET(reg, 0, 5) |
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| 125 | #define ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) |
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| 126 | uint32_t reserved_3c[2]; |
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| 127 | uint32_t tx_fifo_trg_lvl; |
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| 128 | #define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val) BSP_FLD32(val, 0, 5) |
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| 129 | #define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5) |
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| 130 | #define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) |
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| 131 | } zynq_uart; |
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| 132 | |
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| 133 | #endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */ |
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