source: rtems/c/src/lib/libbsp/arm/xilinx-zynq/include/irq.h @ db42c079

4.11
Last change on this file since db42c079 was db42c079, checked in by Sebastian Huber <sebastian.huber@…>, on May 31, 2013 at 11:59:47 AM

bsps/arm: Add SMP support

  • Property mode set to 100644
File size: 2.4 KB
Line 
1/*
2 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
16#define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
17
18#ifndef ASM
19
20#include <rtems/irq.h>
21#include <rtems/irq-extension.h>
22
23#include <bsp/arm-a9mpcore-irq.h>
24#include <bsp/arm-gic-irq.h>
25
26#ifdef __cplusplus
27extern "C" {
28#endif /* __cplusplus */
29
30#define ZYNQ_IRQ_CPU_0 32
31#define ZYNQ_IRQ_CPU_1 33
32#define ZYNQ_IRQ_L2_CACHE 34
33#define ZYNQ_IRQ_OCM 35
34#define ZYNQ_IRQ_PMU_0 37
35#define ZYNQ_IRQ_PMU_1 38
36#define ZYNQ_IRQ_XADC 39
37#define ZYNQ_IRQ_DVI 40
38#define ZYNQ_IRQ_SWDT 41
39#define ZYNQ_IRQ_TTC_0_0 42
40#define ZYNQ_IRQ_TTC_1_0 43
41#define ZYNQ_IRQ_TTC_2_0 44
42#define ZYNQ_IRQ_DMAC_ABORT 45
43#define ZYNQ_IRQ_DMAC_0 46
44#define ZYNQ_IRQ_DMAC_1 47
45#define ZYNQ_IRQ_DMAC_2 48
46#define ZYNQ_IRQ_DMAC_3 49
47#define ZYNQ_IRQ_SMC 50
48#define ZYNQ_IRQ_QUAD_SPI 51
49#define ZYNQ_IRQ_GPIO 52
50#define ZYNQ_IRQ_USB_0 53
51#define ZYNQ_IRQ_ETHERNET_0 54
52#define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55
53#define ZYNQ_IRQ_SDIO_0 56
54#define ZYNQ_IRQ_I2C_0 57
55#define ZYNQ_IRQ_SPI_0 58
56#define ZYNQ_IRQ_UART_0 59
57#define ZYNQ_IRQ_CAN_0 60
58#define ZYNQ_IRQ_FPGA_0 61
59#define ZYNQ_IRQ_FPGA_1 62
60#define ZYNQ_IRQ_FPGA_2 63
61#define ZYNQ_IRQ_FPGA_3 64
62#define ZYNQ_IRQ_FPGA_4 65
63#define ZYNQ_IRQ_FPGA_5 66
64#define ZYNQ_IRQ_FPGA_6 67
65#define ZYNQ_IRQ_FPGA_7 68
66#define ZYNQ_IRQ_TTC_0_1 69
67#define ZYNQ_IRQ_TTC_1_1 70
68#define ZYNQ_IRQ_TTC_2_1 71
69#define ZYNQ_IRQ_DMAC_4 72
70#define ZYNQ_IRQ_DMAC_5 73
71#define ZYNQ_IRQ_DMAC_6 74
72#define ZYNQ_IRQ_DMAC_7 75
73#define ZYNQ_IRQ_USB_1 76
74#define ZYNQ_IRQ_ETHERNET_1 77
75#define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78
76#define ZYNQ_IRQ_SDIO_1 79
77#define ZYNQ_IRQ_I2C_1 80
78#define ZYNQ_IRQ_SPI_1 81
79#define ZYNQ_IRQ_UART_1 82
80#define ZYNQ_IRQ_CAN_1 83
81#define ZYNQ_IRQ_FPGA_8 84
82#define ZYNQ_IRQ_FPGA_9 85
83#define ZYNQ_IRQ_FPGA_10 86
84#define ZYNQ_IRQ_FPGA_11 87
85#define ZYNQ_IRQ_FPGA_12 88
86#define ZYNQ_IRQ_FPGA_13 89
87#define ZYNQ_IRQ_FPGA_14 90
88#define ZYNQ_IRQ_FPGA_15 91
89#define ZYNQ_IRQ_PARITY 92
90
91#define BSP_INTERRUPT_VECTOR_MIN 0
92#define BSP_INTERRUPT_VECTOR_MAX 92
93
94#ifdef __cplusplus
95}
96#endif /* __cplusplus */
97
98#endif /* ASM */
99
100#endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */
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