1 | /* |
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2 | * Copyright (c) 2014 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H |
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16 | #define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H |
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17 | |
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18 | #include <bsp/utility.h> |
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19 | |
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20 | typedef struct { |
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21 | uint32_t control; |
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22 | #define CADENCE_I2C_CONTROL_DIV_A(val) BSP_FLD32(val, 14, 15) |
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23 | #define CADENCE_I2C_CONTROL_DIV_A_GET(reg) BSP_FLD32GET(reg, 14, 15) |
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24 | #define CADENCE_I2C_CONTROL_DIV_A_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15) |
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25 | #define CADENCE_I2C_CONTROL_DIV_B(val) BSP_FLD32(val, 8, 13) |
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26 | #define CADENCE_I2C_CONTROL_DIV_B_GET(reg) BSP_FLD32GET(reg, 8, 13) |
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27 | #define CADENCE_I2C_CONTROL_DIV_B_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13) |
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28 | #define CADENCE_I2C_CONTROL_CLR_FIFO BSP_BIT32(6) |
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29 | #define CADENCE_I2C_CONTROL_SLVMON BSP_BIT32(5) |
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30 | #define CADENCE_I2C_CONTROL_HOLD BSP_BIT32(4) |
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31 | #define CADENCE_I2C_CONTROL_ACKEN BSP_BIT32(3) |
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32 | #define CADENCE_I2C_CONTROL_NEA BSP_BIT32(2) |
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33 | #define CADENCE_I2C_CONTROL_MS BSP_BIT32(1) |
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34 | #define CADENCE_I2C_CONTROL_RW BSP_BIT32(0) |
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35 | uint32_t status; |
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36 | #define CADENCE_I2C_STATUS_BA BSP_BIT32(8) |
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37 | #define CADENCE_I2C_STATUS_RXOVF BSP_BIT32(7) |
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38 | #define CADENCE_I2C_STATUS_TXDV BSP_BIT32(6) |
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39 | #define CADENCE_I2C_STATUS_RXDV BSP_BIT32(5) |
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40 | #define CADENCE_I2C_STATUS_RXRW BSP_BIT32(3) |
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41 | uint32_t address; |
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42 | #define CADENCE_I2C_ADDRESS(val) BSP_FLD32(val, 0, 9) |
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43 | #define CADENCE_I2C_ADDRESS_GET(reg) BSP_FLD32GET(reg, 0, 9) |
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44 | #define CADENCE_I2C_ADDRESS_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) |
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45 | uint32_t data; |
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46 | uint32_t irqstatus; |
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47 | #define CADENCE_I2C_IXR_ARB_LOST BSP_BIT32(9) |
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48 | #define CADENCE_I2C_IXR_RX_UNF BSP_BIT32(7) |
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49 | #define CADENCE_I2C_IXR_TX_OVR BSP_BIT32(6) |
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50 | #define CADENCE_I2C_IXR_RX_OVR BSP_BIT32(5) |
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51 | #define CADENCE_I2C_IXR_SLV_RDY BSP_BIT32(4) |
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52 | #define CADENCE_I2C_IXR_TO BSP_BIT32(3) |
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53 | #define CADENCE_I2C_IXR_NACK BSP_BIT32(2) |
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54 | #define CADENCE_I2C_IXR_DATA BSP_BIT32(1) |
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55 | #define CADENCE_I2C_IXR_COMP BSP_BIT32(0) |
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56 | uint32_t transfer_size; |
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57 | #define CADENCE_I2C_TRANSFER_SIZE(val) BSP_FLD32(val, 0, 7) |
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58 | #define CADENCE_I2C_TRANSFER_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 7) |
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59 | #define CADENCE_I2C_TRANSFER_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) |
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60 | uint32_t slave_mon_pause; |
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61 | #define CADENCE_I2C_SLAVE_MON_PAUSE(val) BSP_FLD32(val, 0, 3) |
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62 | #define CADENCE_I2C_SLAVE_MON_PAUSE_GET(reg) BSP_FLD32GET(reg, 0, 3) |
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63 | #define CADENCE_I2C_SLAVE_MON_PAUSE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) |
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64 | uint32_t timeout; |
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65 | #define CADENCE_I2C_TIMEOUT(val) BSP_FLD32(val, 0, 7) |
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66 | #define CADENCE_I2C_TIMEOUT_GET(reg) BSP_FLD32GET(reg, 0, 7) |
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67 | #define CADENCE_I2C_TIMEOUT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) |
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68 | uint32_t irqmask; |
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69 | uint32_t irqenable; |
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70 | uint32_t irqdisable; |
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71 | } cadence_i2c; |
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72 | |
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73 | #endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H */ |
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