source: rtems/c/src/lib/libbsp/arm/xilinx-zynq/include/cadence-i2c-regs.h @ 45a63ee

4.115
Last change on this file since 45a63ee was 45a63ee, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 10, 2014 at 12:46:32 PM

bsp/xilinx-zynq: Add Cadence I2C bus driver

  • Property mode set to 100644
File size: 2.9 KB
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1/*
2 * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H
16#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H
17
18#include <bsp/utility.h>
19
20typedef struct {
21        uint32_t control;
22#define CADENCE_I2C_CONTROL_DIV_A(val) BSP_FLD32(val, 14, 15)
23#define CADENCE_I2C_CONTROL_DIV_A_GET(reg) BSP_FLD32GET(reg, 14, 15)
24#define CADENCE_I2C_CONTROL_DIV_A_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15)
25#define CADENCE_I2C_CONTROL_DIV_B(val) BSP_FLD32(val, 8, 13)
26#define CADENCE_I2C_CONTROL_DIV_B_GET(reg) BSP_FLD32GET(reg, 8, 13)
27#define CADENCE_I2C_CONTROL_DIV_B_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13)
28#define CADENCE_I2C_CONTROL_CLR_FIFO BSP_BIT32(6)
29#define CADENCE_I2C_CONTROL_SLVMON BSP_BIT32(5)
30#define CADENCE_I2C_CONTROL_HOLD BSP_BIT32(4)
31#define CADENCE_I2C_CONTROL_ACKEN BSP_BIT32(3)
32#define CADENCE_I2C_CONTROL_NEA BSP_BIT32(2)
33#define CADENCE_I2C_CONTROL_MS BSP_BIT32(1)
34#define CADENCE_I2C_CONTROL_RW BSP_BIT32(0)
35        uint32_t status;
36#define CADENCE_I2C_STATUS_BA BSP_BIT32(8)
37#define CADENCE_I2C_STATUS_RXOVF BSP_BIT32(7)
38#define CADENCE_I2C_STATUS_TXDV BSP_BIT32(6)
39#define CADENCE_I2C_STATUS_RXDV BSP_BIT32(5)
40#define CADENCE_I2C_STATUS_RXRW BSP_BIT32(3)
41        uint32_t address;
42#define CADENCE_I2C_ADDRESS(val) BSP_FLD32(val, 0, 9)
43#define CADENCE_I2C_ADDRESS_GET(reg) BSP_FLD32GET(reg, 0, 9)
44#define CADENCE_I2C_ADDRESS_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
45        uint32_t data;
46        uint32_t irqstatus;
47#define CADENCE_I2C_IXR_ARB_LOST BSP_BIT32(9)
48#define CADENCE_I2C_IXR_RX_UNF BSP_BIT32(7)
49#define CADENCE_I2C_IXR_TX_OVR BSP_BIT32(6)
50#define CADENCE_I2C_IXR_RX_OVR BSP_BIT32(5)
51#define CADENCE_I2C_IXR_SLV_RDY BSP_BIT32(4)
52#define CADENCE_I2C_IXR_TO BSP_BIT32(3)
53#define CADENCE_I2C_IXR_NACK BSP_BIT32(2)
54#define CADENCE_I2C_IXR_DATA BSP_BIT32(1)
55#define CADENCE_I2C_IXR_COMP BSP_BIT32(0)
56        uint32_t transfer_size;
57#define CADENCE_I2C_TRANSFER_SIZE(val) BSP_FLD32(val, 0, 7)
58#define CADENCE_I2C_TRANSFER_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 7)
59#define CADENCE_I2C_TRANSFER_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
60        uint32_t slave_mon_pause;
61#define CADENCE_I2C_SLAVE_MON_PAUSE(val) BSP_FLD32(val, 0, 3)
62#define CADENCE_I2C_SLAVE_MON_PAUSE_GET(reg) BSP_FLD32GET(reg, 0, 3)
63#define CADENCE_I2C_SLAVE_MON_PAUSE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
64        uint32_t timeout;
65#define CADENCE_I2C_TIMEOUT(val) BSP_FLD32(val, 0, 7)
66#define CADENCE_I2C_TIMEOUT_GET(reg) BSP_FLD32GET(reg, 0, 7)
67#define CADENCE_I2C_TIMEOUT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
68        uint32_t irqmask;
69        uint32_t irqenable;
70        uint32_t irqdisable;
71} cadence_i2c;
72
73#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H */
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