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1 | /* |
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2 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.com/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #ifndef LIBBSP_ARM_XILINX_ZYNQ_BSP_H |
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16 | #define LIBBSP_ARM_XILINX_ZYNQ_BSP_H |
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17 | |
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18 | #include <bspopts.h> |
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19 | |
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20 | #define BSP_FEATURE_IRQ_EXTENSION |
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21 | |
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22 | #ifndef ASM |
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23 | |
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24 | #include <rtems.h> |
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25 | #include <rtems/console.h> |
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26 | #include <rtems/clockdrv.h> |
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27 | |
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28 | #include <bsp/default-initial-extension.h> |
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29 | |
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30 | #ifdef __cplusplus |
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31 | extern "C" { |
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32 | #endif /* __cplusplus */ |
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33 | |
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34 | #define BSP_ARM_A9MPCORE_SCU_BASE 0xf8f00000 |
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35 | |
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36 | #define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100 |
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37 | |
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38 | #define BSP_ARM_A9MPCORE_PT_BASE 0xf8f00600 |
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39 | |
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40 | #define BSP_ARM_GIC_DIST_BASE 0xf8f01000 |
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41 | |
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42 | typedef enum { |
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43 | BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL, |
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44 | BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE |
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45 | } zynq_fatal_code; |
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46 | |
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47 | void zynq_fatal(zynq_fatal_code code) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
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48 | |
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49 | #ifdef __cplusplus |
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50 | } |
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51 | #endif /* __cplusplus */ |
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52 | |
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53 | #endif /* ASM */ |
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54 | |
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55 | #endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */ |
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