source: rtems/c/src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c @ a94d46c8

4.115
Last change on this file since a94d46c8 was a94d46c8, checked in by Sebastian Huber <sebastian.huber@…>, on May 6, 2013 at 12:34:55 PM

bsp/xilinx-zynq: New BSP

  • Property mode set to 100644
File size: 3.1 KB
Line 
1/*
2 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#include <bsp/zynq-uart.h>
16#include <bsp/zynq-uart-regs.h>
17
18#include <libchip/sersupp.h>
19
20static volatile zynq_uart *zynq_uart_get_regs(int minor)
21{
22  const console_tbl *ct = Console_Port_Tbl != NULL ?
23    Console_Port_Tbl[minor] : &Console_Configuration_Ports[minor];
24
25  return (volatile zynq_uart *) ct->ulCtrlPort1;
26}
27
28static void zynq_uart_initialize(int minor)
29{
30  volatile zynq_uart *regs = zynq_uart_get_regs(minor);
31
32  regs->control = ZYNQ_UART_CONTROL_RXDIS
33    | ZYNQ_UART_CONTROL_TXDIS
34    | ZYNQ_UART_CONTROL_RXRES
35    | ZYNQ_UART_CONTROL_TXRES;
36  regs->mode = ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL)
37    | ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE)
38    | ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
39  regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(1);
40  regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(0xff);
41  regs->rx_fifo_trg_lvl = ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(0);
42  regs->rx_timeout = ZYNQ_UART_RX_TIMEOUT_RTO(0);
43  regs->control = ZYNQ_UART_CONTROL_RXEN
44    | ZYNQ_UART_CONTROL_TXEN
45    | ZYNQ_UART_CONTROL_STTBRK
46    | ZYNQ_UART_CONTROL_RSTTO;
47}
48
49static int zynq_uart_first_open(int major, int minor, void *arg)
50{
51  rtems_libio_open_close_args_t *oc = (rtems_libio_open_close_args_t *) arg;
52  struct rtems_termios_tty *tty = (struct rtems_termios_tty *) oc->iop->data1;
53  console_data *cd = &Console_Port_Data[minor];
54  const console_tbl *ct = Console_Port_Tbl[minor];
55
56  cd->termios_data = tty;
57  rtems_termios_set_initial_baud(tty, (rtems_termios_baud_t) ct->pDeviceParams);
58
59  return 0;
60}
61
62static int zynq_uart_last_close(int major, int minor, void *arg)
63{
64  return 0;
65}
66
67static int zynq_uart_read_polled(int minor)
68{
69  volatile zynq_uart *regs = zynq_uart_get_regs(minor);
70
71  if ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_REMPTY) != 0) {
72    return -1;
73  } else {
74    return ZYNQ_UART_TX_RX_FIFO_FIFO_GET(regs->tx_rx_fifo);
75  }
76}
77
78static void zynq_uart_write_polled(int minor, char c)
79{
80  volatile zynq_uart *regs = zynq_uart_get_regs(minor);
81
82  while ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_TFUL) != 0) {
83    /* Wait */
84  }
85
86  regs->tx_rx_fifo = ZYNQ_UART_TX_RX_FIFO_FIFO(c);
87}
88
89static ssize_t zynq_uart_write_support_polled(
90  int minor,
91  const char *s,
92  size_t n
93)
94{
95  ssize_t i = 0;
96
97  for (i = 0; i < n; ++i) {
98    zynq_uart_write_polled(minor, s[i]);
99  }
100
101  return n;
102}
103
104static int zynq_uart_set_attribues(int minor, const struct termios *term)
105{
106  return -1;
107}
108
109const console_fns zynq_uart_fns = {
110  .deviceProbe = libchip_serial_default_probe,
111  .deviceFirstOpen = zynq_uart_first_open,
112  .deviceLastClose = zynq_uart_last_close,
113  .deviceRead = zynq_uart_read_polled,
114  .deviceWrite = zynq_uart_write_support_polled,
115  .deviceInitialize = zynq_uart_initialize,
116  .deviceWritePolled = zynq_uart_write_polled,
117  .deviceSetAttributes = zynq_uart_set_attribues,
118  .deviceOutputUsesInterrupts = false
119};
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