source: rtems/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac @ d2efc968

5
Last change on this file since d2efc968 was d2efc968, checked in by Sebastian Huber <sebastian.huber@…>, on 10/23/19 at 12:16:47

bsp/xilinx-zynq: Simplify linkcmds config

Use NULL-pointer protection also for Qemu variant.

Do all calculations in the linker command file. This is a preparation
for the new build system.

  • Property mode set to 100644
File size: 4.3 KB
Line 
1##
2#
3# @file
4#
5# @brief Configure script of LibBSP for the Xilinx Zynq platform.
6#
7
8AC_PREREQ([2.69])
9AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
10RTEMS_TOP(../../../../../..)
11RTEMS_SOURCE_TOP
12RTEMS_BUILD_TOP
13
14RTEMS_CANONICAL_TARGET_CPU
15AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
16RTEMS_BSP_CONFIGURE
17
18
19
20RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
21RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
22
23RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*qemu],[])
24RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1])
25RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache])
26
27RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*qemu],[])
28RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1])
29RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache])
30
31RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zc702*],[333333333U])
32RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zedboard*],[666666667U])
33RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U])
34RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz])
35
36RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zc702*],[50000000UL])
37RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zedboard*],[50000000UL])
38RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[*],[50000000UL])
39RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_UART],[Zynq UART clock frequency in Hz])
40
41RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zc702*],[111111111U])
42RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zedboard*],[111111111U])
43RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[*],[111111111U])
44RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_CPU_1X],[Zynq cpu_1x clock frequency in Hz])
45
46USE_FAST_IDLE=0
47AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], [USE_FAST_IDLE=1])
48
49RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[${USE_FAST_IDLE}])
50RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_FAST_IDLE],
51[This sets a mode where the time runs as fast as possible when a clock ISR
52occurs while the IDLE thread is executing.  This can significantly reduce
53simulation times.])
54
55RTEMS_BSPOPTS_SET([BSP_CONSOLE_MINOR],[*],[1])
56RTEMS_BSPOPTS_HELP([BSP_CONSOLE_MINOR],[minor number of console device])
57
58RTEMS_BSPOPTS_SET([ZYNQ_CONSOLE_USE_INTERRUPTS],[*],[1])
59RTEMS_BSPOPTS_HELP([ZYNQ_CONSOLE_USE_INTERRUPTS],[use interrupt driven mode for console devices (used by default)])
60
61#
62# Zynq Memory map can be controlled from the configure command line. Use ...
63#
64#   ..../configure --target=arm-rtems4.11 ... BSP_ZYNQ_RAM_LENGTH=256M
65#
66RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_a9_qemu],[256M])
67RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc702],[1024M])
68RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc706],[1024M])
69RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zedboard],[512M])
70RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[*],[256M])
71RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length])
72
73RTEMS_BSPOPTS_SET([BSP_ZYNQ_NOCACHE_LENGTH],[*],[1M])
74RTEMS_BSPOPTS_HELP([BSP_ZYNQ_NOCACHE_LENGTH],[length of nocache RAM region])
75
76ZYNQ_RAM_ORIGIN="0x00100000"
77ZYNQ_RAM_MMU_LENGTH="16k"
78ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
79ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
80ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
81ZYNQ_RAM_INT_1_LENGTH="64k - 512"
82
83AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc706],
84      [ZYNQ_RAM_ORIGIN="0x00400000"])
85
86AC_DEFUN([ZYNQ_LINKCMD],[
87AC_ARG_VAR([$1],[$2; default $3])dnl
88[$1]=[$]{[$1]:-[$3]}
89])
90
91ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN],[normal RAM region origin],[${ZYNQ_RAM_ORIGIN}])
92ZYNQ_LINKCMD([BSP_ZYNQ_RAM_LENGTH],[normal RAM region length],[${BSP_ZYNQ_RAM_LENGTH}])
93ZYNQ_LINKCMD([ZYNQ_RAM_MMU_LENGTH],[MMU region length],[${ZYNQ_RAM_MMU_LENGTH}])
94ZYNQ_LINKCMD([ZYNQ_RAM_NOCACHE_LENGTH],[length of nocache RAM region],[${BSP_ZYNQ_NOCACHE_LENGTH}])
95ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_ORIGIN],[internal 0 RAM region origin],[${ZYNQ_RAM_INT_0_ORIGIN}])
96ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_LENGTH],[internal 0 RAM region length],[${ZYNQ_RAM_INT_0_LENGTH}])
97ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_ORIGIN],[internal 1 RAM region origin],[${ZYNQ_RAM_INT_1_ORIGIN}])
98ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_LENGTH],[internal 1 RAM region length],[${ZYNQ_RAM_INT_1_LENGTH}])
99
100RTEMS_BSP_CLEANUP_OPTIONS
101
102AC_CONFIG_FILES([
103Makefile
104linkcmds:../../../../../../bsps/arm/xilinx-zynq/start/linkcmds.in])
105AC_OUTPUT
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