source: rtems/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac @ 78c9fe8

5
Last change on this file since 78c9fe8 was 12072880, checked in by Sebastian Huber <sebastian.huber@…>, on Dec 4, 2014 at 9:03:50 AM

Update bug report URL

  • Property mode set to 100644
File size: 6.2 KB
Line 
1##
2#
3# @file
4#
5# @brief Configure script of LibBSP for the Xilinx Zynq platform.
6#
7
8AC_PREREQ([2.69])
9AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
10AC_CONFIG_SRCDIR([bsp_specs])
11RTEMS_TOP(../../../../../..)
12
13RTEMS_CANONICAL_TARGET_CPU
14AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
15RTEMS_BSP_CONFIGURE
16
17RTEMS_PROG_CC_FOR_TARGET
18RTEMS_CANONICALIZE_TOOLS
19RTEMS_PROG_CCAS
20
21RTEMS_CHECK_NETWORKING
22AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
23
24RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
25RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
26
27RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*qemu],[])
28RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1])
29RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache])
30
31RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*qemu],[])
32RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1])
33RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache])
34
35RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zc702*],[333333333U])
36RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zedboard*],[666666667U])
37RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U])
38RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz])
39
40RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zc702*],[50000000UL])
41RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zedboard*],[50000000UL])
42RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[*],[50000000UL])
43RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_UART],[Zynq UART clock frequency in Hz])
44
45RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zc702*],[111111111U])
46RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zedboard*],[111111111U])
47RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[*],[111111111U])
48RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_CPU_1X],[Zynq cpu_1x clock frequency in Hz])
49
50USE_FAST_IDLE=0
51AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], [USE_FAST_IDLE=1])
52
53RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[${USE_FAST_IDLE}])
54RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_FAST_IDLE],
55[This sets a mode where the time runs as fast as possible when a clock ISR
56occurs while the IDLE thread is executing.  This can significantly reduce
57simulation times.])
58
59RTEMS_BSPOPTS_SET([BSP_CONSOLE_MINOR],[*],[1])
60RTEMS_BSPOPTS_HELP([BSP_CONSOLE_MINOR],[minor number of console device])
61
62ZYNQ_CPUS="1"
63RTEMS_CHECK_SMP
64AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"])
65AS_IF([test "$rtems_cv_HAS_SMP" = "yes"],
66      [ZYNQ_CPUS="2"])
67
68#
69# Zynq Memory map can be controlled from the configure command line. Use ...
70#
71#   ..../configure --target=arm-rtems4.11 ... BSP_ZYNQ_RAM_LENGTH=256M
72#
73RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_a9_qemu],[256M])
74RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc702],[1024M])
75RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc706],[1024M])
76RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zedboard],[512M])
77RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[*],[256M])
78RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length])
79
80RTEMS_BSPOPTS_SET([BSP_ZYNQ_NOCACHE_LENGTH],[*],[1M])
81RTEMS_BSPOPTS_HELP([BSP_ZYNQ_NOCACHE_LENGTH],[length of nocache RAM region])
82
83AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu],
84      [ZYNQ_RAM_ORIGIN="0x00000000"
85       ZYNQ_RAM_MMU="0x0fffc000"
86       ZYNQ_RAM_MMU_LENGTH="16k"
87       ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN}"
88       ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 16k"
89       ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
90       ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
91       ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
92       ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
93
94AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc702],
95      [ZYNQ_RAM_ORIGIN="0x00100000"
96       ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
97       ZYNQ_RAM_MMU_LENGTH="16k"
98       ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
99       ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"
100       ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
101       ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
102       ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
103       ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
104
105AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc706],
106      [ZYNQ_RAM_ORIGIN="0x00400000"
107       ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
108       ZYNQ_RAM_MMU_LENGTH="16k"
109       ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
110       ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k"
111       ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
112       ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
113       ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
114       ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
115
116AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zedboard],
117      [ZYNQ_RAM_ORIGIN="0x00100000"
118       ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
119       ZYNQ_RAM_MMU_LENGTH="16k"
120       ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
121       ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"
122       ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
123       ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
124       ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
125       ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
126
127AC_DEFUN([ZYNQ_LINKCMD],[
128AC_ARG_VAR([$1],[$2; default $3])dnl
129[$1]=[$]{[$1]:-[$3]}
130])
131
132ZYNQ_LINKCMD([ZYNQ_CPUS],[Number of active cores],[${ZYNQ_CPUS}])
133ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN],[normal RAM region origin],[${ZYNQ_RAM_ORIGIN}])
134ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH],[normal RAM region length],[${BSP_ZYNQ_RAM_LENGTH}])
135ZYNQ_LINKCMD([ZYNQ_RAM_MMU],[MMU region origin],[${ZYNQ_RAM_MMU}])
136ZYNQ_LINKCMD([ZYNQ_RAM_MMU_LENGTH],[MMU region length],[${ZYNQ_RAM_MMU_LENGTH}])
137ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN_AVAILABLE],[origin of available RAM],[${ZYNQ_RAM_ORIGIN_AVAILABLE}])
138ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH_AVAILABLE],[length of available RAM],[${ZYNQ_RAM_LENGTH_AVAILABLE}])
139ZYNQ_LINKCMD([ZYNQ_RAM_NOCACHE_LENGTH],[length of nocache RAM region],[${BSP_ZYNQ_NOCACHE_LENGTH}])
140ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_ORIGIN],[internal 0 RAM region origin],[${ZYNQ_RAM_INT_0_ORIGIN}])
141ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_LENGTH],[internal 0 RAM region length],[${ZYNQ_RAM_INT_0_LENGTH}])
142ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_ORIGIN],[internal 1 RAM region origin],[${ZYNQ_RAM_INT_1_ORIGIN}])
143ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_LENGTH],[internal 1 RAM region length],[${ZYNQ_RAM_INT_1_LENGTH}])
144
145RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
146
147AC_CONFIG_FILES([
148Makefile
149startup/linkcmds])
150AC_OUTPUT
Note: See TracBrowser for help on using the repository browser.