1 | ## |
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2 | # |
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3 | # @file |
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4 | # |
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5 | # @brief Configure script of LibBSP for the Xilinx Zynq platform. |
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6 | # |
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7 | |
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8 | AC_PREREQ([2.69]) |
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9 | AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) |
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10 | AC_CONFIG_SRCDIR([bsp_specs]) |
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11 | RTEMS_TOP(../../../../../..) |
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12 | |
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13 | RTEMS_CANONICAL_TARGET_CPU |
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14 | AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) |
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15 | RTEMS_BSP_CONFIGURE |
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16 | |
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17 | RTEMS_PROG_CC_FOR_TARGET |
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18 | RTEMS_CANONICALIZE_TOOLS |
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19 | RTEMS_PROG_CCAS |
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20 | |
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21 | RTEMS_CHECK_NETWORKING |
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22 | AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") |
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23 | |
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24 | RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) |
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25 | RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) |
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26 | |
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27 | RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*qemu],[]) |
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28 | RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1]) |
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29 | RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache]) |
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30 | |
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31 | RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*qemu],[]) |
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32 | RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1]) |
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33 | RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache]) |
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34 | |
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35 | RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zc702*],[333333333U]) |
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36 | RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zedboard*],[666666667U]) |
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37 | RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U]) |
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38 | RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz]) |
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39 | |
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40 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zc702*],[50000000UL]) |
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41 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zedboard*],[50000000UL]) |
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42 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[*],[50000000UL]) |
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43 | RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_UART],[Zynq UART clock frequency in Hz]) |
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44 | |
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45 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zc702*],[111111111U]) |
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46 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zedboard*],[111111111U]) |
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47 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[*],[111111111U]) |
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48 | RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_CPU_1X],[Zynq cpu_1x clock frequency in Hz]) |
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49 | |
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50 | USE_FAST_IDLE=0 |
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51 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], [USE_FAST_IDLE=1]) |
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52 | |
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53 | RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[${USE_FAST_IDLE}]) |
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54 | RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_FAST_IDLE], |
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55 | [This sets a mode where the time runs as fast as possible when a clock ISR |
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56 | occurs while the IDLE thread is executing. This can significantly reduce |
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57 | simulation times.]) |
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58 | |
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59 | RTEMS_BSPOPTS_SET([BSP_CONSOLE_MINOR],[*],[1]) |
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60 | RTEMS_BSPOPTS_HELP([BSP_CONSOLE_MINOR],[minor number of console device]) |
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61 | |
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62 | ZYNQ_CPUS="1" |
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63 | RTEMS_CHECK_SMP |
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64 | AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"]) |
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65 | AS_IF([test "$rtems_cv_HAS_SMP" = "yes"], |
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66 | [ZYNQ_CPUS="2"]) |
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67 | |
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68 | # |
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69 | # Zynq Memory map can be controlled from the configure command line. Use ... |
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70 | # |
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71 | # ..../configure --target=arm-rtems4.11 ... BSP_ZYNQ_RAM_LENGTH=256M |
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72 | # |
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73 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_a9_qemu],[256M]) |
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74 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc702],[1024M]) |
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75 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc706],[1024M]) |
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76 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zedboard],[512M]) |
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77 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[*],[256M]) |
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78 | RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length]) |
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79 | |
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80 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_NOCACHE_LENGTH],[*],[1M]) |
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81 | RTEMS_BSPOPTS_HELP([BSP_ZYNQ_NOCACHE_LENGTH],[length of nocache RAM region]) |
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82 | |
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83 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], |
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84 | [ZYNQ_RAM_ORIGIN="0x00000000" |
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85 | ZYNQ_RAM_MMU="0x0fffc000" |
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86 | ZYNQ_RAM_MMU_LENGTH="16k" |
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87 | ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN}" |
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88 | ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 16k" |
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89 | ZYNQ_RAM_INT_0_ORIGIN="0x00000000" |
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90 | ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" |
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91 | ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" |
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92 | ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) |
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93 | |
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94 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc702], |
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95 | [ZYNQ_RAM_ORIGIN="0x00100000" |
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96 | ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" |
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97 | ZYNQ_RAM_MMU_LENGTH="16k" |
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98 | ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" |
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99 | ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k" |
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100 | ZYNQ_RAM_INT_0_ORIGIN="0x00000000" |
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101 | ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" |
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102 | ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" |
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103 | ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) |
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104 | |
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105 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc706], |
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106 | [ZYNQ_RAM_ORIGIN="0x00400000" |
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107 | ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" |
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108 | ZYNQ_RAM_MMU_LENGTH="16k" |
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109 | ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" |
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110 | ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k" |
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111 | ZYNQ_RAM_INT_0_ORIGIN="0x00000000" |
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112 | ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" |
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113 | ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" |
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114 | ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) |
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115 | |
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116 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zedboard], |
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117 | [ZYNQ_RAM_ORIGIN="0x00100000" |
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118 | ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" |
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119 | ZYNQ_RAM_MMU_LENGTH="16k" |
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120 | ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" |
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121 | ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k" |
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122 | ZYNQ_RAM_INT_0_ORIGIN="0x00000000" |
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123 | ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" |
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124 | ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" |
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125 | ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) |
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126 | |
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127 | AC_DEFUN([ZYNQ_LINKCMD],[ |
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128 | AC_ARG_VAR([$1],[$2; default $3])dnl |
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129 | [$1]=[$]{[$1]:-[$3]} |
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130 | ]) |
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131 | |
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132 | ZYNQ_LINKCMD([ZYNQ_CPUS],[Number of active cores],[${ZYNQ_CPUS}]) |
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133 | ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN],[normal RAM region origin],[${ZYNQ_RAM_ORIGIN}]) |
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134 | ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH],[normal RAM region length],[${BSP_ZYNQ_RAM_LENGTH}]) |
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135 | ZYNQ_LINKCMD([ZYNQ_RAM_MMU],[MMU region origin],[${ZYNQ_RAM_MMU}]) |
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136 | ZYNQ_LINKCMD([ZYNQ_RAM_MMU_LENGTH],[MMU region length],[${ZYNQ_RAM_MMU_LENGTH}]) |
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137 | ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN_AVAILABLE],[origin of available RAM],[${ZYNQ_RAM_ORIGIN_AVAILABLE}]) |
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138 | ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH_AVAILABLE],[length of available RAM],[${ZYNQ_RAM_LENGTH_AVAILABLE}]) |
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139 | ZYNQ_LINKCMD([ZYNQ_RAM_NOCACHE_LENGTH],[length of nocache RAM region],[${BSP_ZYNQ_NOCACHE_LENGTH}]) |
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140 | ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_ORIGIN],[internal 0 RAM region origin],[${ZYNQ_RAM_INT_0_ORIGIN}]) |
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141 | ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_LENGTH],[internal 0 RAM region length],[${ZYNQ_RAM_INT_0_LENGTH}]) |
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142 | ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_ORIGIN],[internal 1 RAM region origin],[${ZYNQ_RAM_INT_1_ORIGIN}]) |
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143 | ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_LENGTH],[internal 1 RAM region length],[${ZYNQ_RAM_INT_1_LENGTH}]) |
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144 | |
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145 | RTEMS_BSP_CLEANUP_OPTIONS(0, 1) |
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146 | |
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147 | AC_CONFIG_FILES([ |
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148 | Makefile |
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149 | startup/linkcmds]) |
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150 | AC_OUTPUT |
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