source: rtems/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac @ 511dc4b

5
Last change on this file since 511dc4b was 511dc4b, checked in by Sebastian Huber <sebastian.huber@…>, on 06/19/18 at 07:09:51

Rework initialization and interrupt stack support

Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).

This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.

This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.

Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).

The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.

The initialization stack can reuse the interrupt stack, since

  • interrupts are disabled during the sequential system initialization, and
  • the boot_card() function does not return.

This stack resuse saves memory.

Changes per architecture:

arm:

  • Mostly replace the linker symbol based configuration of stacks with the standard <rtems/confdefs.h> configuration via CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND mode stack is still defined via linker symbols. These modes are rarely used in applications and the default values provided by the BSP should be sufficient in most cases.
  • Remove the bsp_processor_count linker symbol hack used for the SMP support. This is possible since the interrupt stack area is now allocated by the linker and not allocated from the heap. This makes some configure.ac stuff obsolete. Remove the now superfluous BSP variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.

bfin:

  • Remove unused magic linker command file allocation of initialization stack. Maybe a previous linker command file copy and paste problem? In the start.S the initialization stack is set to a hard coded value.

lm32, m32c, mips, nios2, riscv, sh, v850:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.

m68k:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.

powerpc:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.
  • Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt stack on BSPs using the shared linkcmds.base (replacement for REGION_RWEXTRA).

sparc:

  • Remove the hard coded initialization stack. Use the interrupt stack for the initialization stack on the boot processor. This saves 16KiB of RAM.

Update #3459.
  • Property mode set to 100644
File size: 6.1 KB
Line 
1##
2#
3# @file
4#
5# @brief Configure script of LibBSP for the Xilinx Zynq platform.
6#
7
8AC_PREREQ([2.69])
9AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
10RTEMS_TOP(../../../../../..)
11RTEMS_SOURCE_TOP
12RTEMS_BUILD_TOP
13
14RTEMS_CANONICAL_TARGET_CPU
15AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
16RTEMS_BSP_CONFIGURE
17
18
19
20RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
21RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
22
23RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*qemu],[])
24RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1])
25RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache])
26
27RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*qemu],[])
28RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1])
29RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache])
30
31RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zc702*],[333333333U])
32RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zedboard*],[666666667U])
33RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U])
34RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz])
35
36RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zc702*],[50000000UL])
37RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zedboard*],[50000000UL])
38RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[*],[50000000UL])
39RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_UART],[Zynq UART clock frequency in Hz])
40
41RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zc702*],[111111111U])
42RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zedboard*],[111111111U])
43RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[*],[111111111U])
44RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_CPU_1X],[Zynq cpu_1x clock frequency in Hz])
45
46USE_FAST_IDLE=0
47AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], [USE_FAST_IDLE=1])
48
49RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[${USE_FAST_IDLE}])
50RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_FAST_IDLE],
51[This sets a mode where the time runs as fast as possible when a clock ISR
52occurs while the IDLE thread is executing.  This can significantly reduce
53simulation times.])
54
55RTEMS_BSPOPTS_SET([BSP_CONSOLE_MINOR],[*],[1])
56RTEMS_BSPOPTS_HELP([BSP_CONSOLE_MINOR],[minor number of console device])
57
58RTEMS_BSPOPTS_SET([ZYNQ_CONSOLE_USE_INTERRUPTS],[*],[1])
59RTEMS_BSPOPTS_HELP([ZYNQ_CONSOLE_USE_INTERRUPTS],[use interrupt driven mode for console devices (used by default)])
60
61#
62# Zynq Memory map can be controlled from the configure command line. Use ...
63#
64#   ..../configure --target=arm-rtems4.11 ... BSP_ZYNQ_RAM_LENGTH=256M
65#
66RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_a9_qemu],[256M])
67RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc702],[1024M])
68RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc706],[1024M])
69RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zedboard],[512M])
70RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[*],[256M])
71RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length])
72
73RTEMS_BSPOPTS_SET([BSP_ZYNQ_NOCACHE_LENGTH],[*],[1M])
74RTEMS_BSPOPTS_HELP([BSP_ZYNQ_NOCACHE_LENGTH],[length of nocache RAM region])
75
76AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu],
77      [ZYNQ_RAM_ORIGIN="0x00000000"
78       ZYNQ_RAM_MMU="0x0fffc000"
79       ZYNQ_RAM_MMU_LENGTH="16k"
80       ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN}"
81       ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 16k"
82       ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
83       ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
84       ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
85       ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
86
87AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc702],
88      [ZYNQ_RAM_ORIGIN="0x00100000"
89       ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
90       ZYNQ_RAM_MMU_LENGTH="16k"
91       ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
92       ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"
93       ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
94       ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
95       ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
96       ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
97
98AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc706],
99      [ZYNQ_RAM_ORIGIN="0x00400000"
100       ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
101       ZYNQ_RAM_MMU_LENGTH="16k"
102       ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
103       ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k"
104       ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
105       ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
106       ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
107       ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
108
109AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zedboard],
110      [ZYNQ_RAM_ORIGIN="0x00100000"
111       ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
112       ZYNQ_RAM_MMU_LENGTH="16k"
113       ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
114       ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"
115       ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
116       ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
117       ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
118       ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
119
120AC_DEFUN([ZYNQ_LINKCMD],[
121AC_ARG_VAR([$1],[$2; default $3])dnl
122[$1]=[$]{[$1]:-[$3]}
123])
124
125ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN],[normal RAM region origin],[${ZYNQ_RAM_ORIGIN}])
126ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH],[normal RAM region length],[${BSP_ZYNQ_RAM_LENGTH}])
127ZYNQ_LINKCMD([ZYNQ_RAM_MMU],[MMU region origin],[${ZYNQ_RAM_MMU}])
128ZYNQ_LINKCMD([ZYNQ_RAM_MMU_LENGTH],[MMU region length],[${ZYNQ_RAM_MMU_LENGTH}])
129ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN_AVAILABLE],[origin of available RAM],[${ZYNQ_RAM_ORIGIN_AVAILABLE}])
130ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH_AVAILABLE],[length of available RAM],[${ZYNQ_RAM_LENGTH_AVAILABLE}])
131ZYNQ_LINKCMD([ZYNQ_RAM_NOCACHE_LENGTH],[length of nocache RAM region],[${BSP_ZYNQ_NOCACHE_LENGTH}])
132ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_ORIGIN],[internal 0 RAM region origin],[${ZYNQ_RAM_INT_0_ORIGIN}])
133ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_LENGTH],[internal 0 RAM region length],[${ZYNQ_RAM_INT_0_LENGTH}])
134ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_ORIGIN],[internal 1 RAM region origin],[${ZYNQ_RAM_INT_1_ORIGIN}])
135ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_LENGTH],[internal 1 RAM region length],[${ZYNQ_RAM_INT_1_LENGTH}])
136
137RTEMS_BSP_CLEANUP_OPTIONS
138
139AC_CONFIG_FILES([
140Makefile
141linkcmds:../../../../../../bsps/arm/xilinx-zynq/start/linkcmds.in])
142AC_OUTPUT
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