[a94d46c8] | 1 | ## |
---|
| 2 | # |
---|
| 3 | # @file |
---|
| 4 | # |
---|
| 5 | # @brief Configure script of LibBSP for the Xilinx Zynq platform. |
---|
| 6 | # |
---|
| 7 | |
---|
| 8 | AC_PREREQ([2.69]) |
---|
[12072880] | 9 | AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) |
---|
[a94d46c8] | 10 | AC_CONFIG_SRCDIR([bsp_specs]) |
---|
| 11 | RTEMS_TOP(../../../../../..) |
---|
| 12 | |
---|
| 13 | RTEMS_CANONICAL_TARGET_CPU |
---|
| 14 | AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) |
---|
| 15 | RTEMS_BSP_CONFIGURE |
---|
| 16 | |
---|
| 17 | RTEMS_PROG_CC_FOR_TARGET |
---|
| 18 | RTEMS_CANONICALIZE_TOOLS |
---|
| 19 | RTEMS_PROG_CCAS |
---|
| 20 | |
---|
| 21 | RTEMS_CHECK_NETWORKING |
---|
| 22 | AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") |
---|
| 23 | |
---|
| 24 | RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) |
---|
| 25 | RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) |
---|
| 26 | |
---|
[50440c0] | 27 | RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*qemu],[]) |
---|
| 28 | RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1]) |
---|
| 29 | RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache]) |
---|
| 30 | |
---|
| 31 | RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*qemu],[]) |
---|
| 32 | RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1]) |
---|
| 33 | RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache]) |
---|
| 34 | |
---|
[8100e71] | 35 | RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zc702*],[333333333U]) |
---|
[691e0ef] | 36 | RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zedboard*],[666666667U]) |
---|
[a94d46c8] | 37 | RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U]) |
---|
| 38 | RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz]) |
---|
| 39 | |
---|
[234d5c40] | 40 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zc702*],[50000000UL]) |
---|
| 41 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zedboard*],[50000000UL]) |
---|
| 42 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[*],[50000000UL]) |
---|
| 43 | RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_UART],[Zynq UART clock frequency in Hz]) |
---|
[18bd35bc] | 44 | |
---|
[bdf8fa76] | 45 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zc702*],[111111111U]) |
---|
| 46 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zedboard*],[111111111U]) |
---|
| 47 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[*],[111111111U]) |
---|
| 48 | RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_CPU_1X],[Zynq cpu_1x clock frequency in Hz]) |
---|
| 49 | |
---|
[e5d706c] | 50 | USE_FAST_IDLE=0 |
---|
| 51 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], [USE_FAST_IDLE=1]) |
---|
| 52 | |
---|
| 53 | RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[${USE_FAST_IDLE}]) |
---|
[9984acd] | 54 | RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_FAST_IDLE], |
---|
| 55 | [This sets a mode where the time runs as fast as possible when a clock ISR |
---|
| 56 | occurs while the IDLE thread is executing. This can significantly reduce |
---|
| 57 | simulation times.]) |
---|
| 58 | |
---|
[49bc9f81] | 59 | RTEMS_BSPOPTS_SET([BSP_CONSOLE_MINOR],[*],[1]) |
---|
[cf46db85] | 60 | RTEMS_BSPOPTS_HELP([BSP_CONSOLE_MINOR],[minor number of console device]) |
---|
| 61 | |
---|
[e5d706c] | 62 | ZYNQ_CPUS="1" |
---|
[db42c079] | 63 | RTEMS_CHECK_SMP |
---|
| 64 | AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"]) |
---|
[e5d706c] | 65 | AS_IF([test "$rtems_cv_HAS_SMP" = "yes"], |
---|
| 66 | [ZYNQ_CPUS="2"]) |
---|
| 67 | |
---|
| 68 | # |
---|
| 69 | # Zynq Memory map can be controlled from the configure command line. Use ... |
---|
| 70 | # |
---|
[e9d98071] | 71 | # ..../configure --target=arm-rtems4.11 ... BSP_ZYNQ_RAM_LENGTH=256M |
---|
[e5d706c] | 72 | # |
---|
[e9d98071] | 73 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_a9_qemu],[256M]) |
---|
| 74 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc702],[1024M]) |
---|
| 75 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc706],[1024M]) |
---|
| 76 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zedboard],[512M]) |
---|
| 77 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[*],[256M]) |
---|
| 78 | RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length]) |
---|
| 79 | |
---|
[cbc433c7] | 80 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_NOCACHE_LENGTH],[*],[1M]) |
---|
| 81 | RTEMS_BSPOPTS_HELP([BSP_ZYNQ_NOCACHE_LENGTH],[length of nocache RAM region]) |
---|
| 82 | |
---|
[e5d706c] | 83 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], |
---|
| 84 | [ZYNQ_RAM_ORIGIN="0x00000000" |
---|
| 85 | ZYNQ_RAM_MMU="0x0fffc000" |
---|
| 86 | ZYNQ_RAM_MMU_LENGTH="16k" |
---|
| 87 | ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN}" |
---|
[e9d98071] | 88 | ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 16k" |
---|
[e5d706c] | 89 | ZYNQ_RAM_INT_0_ORIGIN="0x00000000" |
---|
| 90 | ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" |
---|
| 91 | ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" |
---|
| 92 | ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) |
---|
| 93 | |
---|
| 94 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc702], |
---|
| 95 | [ZYNQ_RAM_ORIGIN="0x00100000" |
---|
| 96 | ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" |
---|
| 97 | ZYNQ_RAM_MMU_LENGTH="16k" |
---|
| 98 | ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" |
---|
[e9d98071] | 99 | ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k" |
---|
[e5d706c] | 100 | ZYNQ_RAM_INT_0_ORIGIN="0x00000000" |
---|
| 101 | ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" |
---|
| 102 | ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" |
---|
| 103 | ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) |
---|
| 104 | |
---|
| 105 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc706], |
---|
| 106 | [ZYNQ_RAM_ORIGIN="0x00400000" |
---|
| 107 | ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" |
---|
| 108 | ZYNQ_RAM_MMU_LENGTH="16k" |
---|
| 109 | ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" |
---|
[e9d98071] | 110 | ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k" |
---|
[e5d706c] | 111 | ZYNQ_RAM_INT_0_ORIGIN="0x00000000" |
---|
| 112 | ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" |
---|
| 113 | ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" |
---|
| 114 | ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) |
---|
| 115 | |
---|
| 116 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zedboard], |
---|
| 117 | [ZYNQ_RAM_ORIGIN="0x00100000" |
---|
| 118 | ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" |
---|
| 119 | ZYNQ_RAM_MMU_LENGTH="16k" |
---|
| 120 | ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" |
---|
[e9d98071] | 121 | ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k" |
---|
[e5d706c] | 122 | ZYNQ_RAM_INT_0_ORIGIN="0x00000000" |
---|
| 123 | ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" |
---|
| 124 | ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" |
---|
| 125 | ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) |
---|
| 126 | |
---|
| 127 | AC_DEFUN([ZYNQ_LINKCMD],[ |
---|
| 128 | AC_ARG_VAR([$1],[$2; default $3])dnl |
---|
| 129 | [$1]=[$]{[$1]:-[$3]} |
---|
| 130 | ]) |
---|
| 131 | |
---|
| 132 | ZYNQ_LINKCMD([ZYNQ_CPUS],[Number of active cores],[${ZYNQ_CPUS}]) |
---|
| 133 | ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN],[normal RAM region origin],[${ZYNQ_RAM_ORIGIN}]) |
---|
[e9d98071] | 134 | ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH],[normal RAM region length],[${BSP_ZYNQ_RAM_LENGTH}]) |
---|
[e5d706c] | 135 | ZYNQ_LINKCMD([ZYNQ_RAM_MMU],[MMU region origin],[${ZYNQ_RAM_MMU}]) |
---|
| 136 | ZYNQ_LINKCMD([ZYNQ_RAM_MMU_LENGTH],[MMU region length],[${ZYNQ_RAM_MMU_LENGTH}]) |
---|
| 137 | ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN_AVAILABLE],[origin of available RAM],[${ZYNQ_RAM_ORIGIN_AVAILABLE}]) |
---|
| 138 | ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH_AVAILABLE],[length of available RAM],[${ZYNQ_RAM_LENGTH_AVAILABLE}]) |
---|
[cbc433c7] | 139 | ZYNQ_LINKCMD([ZYNQ_RAM_NOCACHE_LENGTH],[length of nocache RAM region],[${BSP_ZYNQ_NOCACHE_LENGTH}]) |
---|
[e5d706c] | 140 | ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_ORIGIN],[internal 0 RAM region origin],[${ZYNQ_RAM_INT_0_ORIGIN}]) |
---|
| 141 | ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_LENGTH],[internal 0 RAM region length],[${ZYNQ_RAM_INT_0_LENGTH}]) |
---|
| 142 | ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_ORIGIN],[internal 1 RAM region origin],[${ZYNQ_RAM_INT_1_ORIGIN}]) |
---|
| 143 | ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_LENGTH],[internal 1 RAM region length],[${ZYNQ_RAM_INT_1_LENGTH}]) |
---|
[db42c079] | 144 | |
---|
[a94d46c8] | 145 | RTEMS_BSP_CLEANUP_OPTIONS(0, 1) |
---|
| 146 | |
---|
[e5d706c] | 147 | AC_CONFIG_FILES([ |
---|
| 148 | Makefile |
---|
| 149 | startup/linkcmds]) |
---|
[a94d46c8] | 150 | AC_OUTPUT |
---|