[a94d46c8] | 1 | ## |
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| 2 | # |
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| 3 | # @file |
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| 4 | # |
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| 5 | # @brief Configure script of LibBSP for the Xilinx Zynq platform. |
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| 6 | # |
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| 7 | |
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| 8 | AC_PREREQ([2.69]) |
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| 9 | AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla]) |
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| 10 | AC_CONFIG_SRCDIR([bsp_specs]) |
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| 11 | RTEMS_TOP(../../../../../..) |
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| 12 | |
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| 13 | RTEMS_CANONICAL_TARGET_CPU |
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| 14 | AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) |
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| 15 | RTEMS_BSP_CONFIGURE |
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| 16 | |
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| 17 | RTEMS_PROG_CC_FOR_TARGET |
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| 18 | RTEMS_CANONICALIZE_TOOLS |
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| 19 | RTEMS_PROG_CCAS |
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| 20 | |
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| 21 | RTEMS_CHECK_NETWORKING |
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| 22 | AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") |
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| 23 | |
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| 24 | RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) |
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| 25 | RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) |
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| 26 | |
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[8100e71] | 27 | RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zc702*],[333333333U]) |
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[691e0ef] | 28 | RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zedboard*],[666666667U]) |
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[a94d46c8] | 29 | RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U]) |
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| 30 | RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz]) |
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| 31 | |
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[234d5c40] | 32 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zc702*],[50000000UL]) |
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| 33 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zedboard*],[50000000UL]) |
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| 34 | RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[*],[50000000UL]) |
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| 35 | RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_UART],[Zynq UART clock frequency in Hz]) |
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[18bd35bc] | 36 | |
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[e5d706c] | 37 | USE_FAST_IDLE=0 |
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| 38 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], [USE_FAST_IDLE=1]) |
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| 39 | |
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| 40 | RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[${USE_FAST_IDLE}]) |
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[9984acd] | 41 | RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_FAST_IDLE], |
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| 42 | [This sets a mode where the time runs as fast as possible when a clock ISR |
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| 43 | occurs while the IDLE thread is executing. This can significantly reduce |
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| 44 | simulation times.]) |
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| 45 | |
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[49bc9f81] | 46 | RTEMS_BSPOPTS_SET([BSP_CONSOLE_MINOR],[*],[1]) |
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[cf46db85] | 47 | RTEMS_BSPOPTS_HELP([BSP_CONSOLE_MINOR],[minor number of console device]) |
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| 48 | |
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[e5d706c] | 49 | ZYNQ_CPUS="1" |
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[db42c079] | 50 | RTEMS_CHECK_SMP |
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| 51 | AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"]) |
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[e5d706c] | 52 | AS_IF([test "$rtems_cv_HAS_SMP" = "yes"], |
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| 53 | [ZYNQ_CPUS="2"]) |
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| 54 | |
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| 55 | # |
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| 56 | # Zynq Memory map can be controlled from the configure command line. Use ... |
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| 57 | # |
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[e9d98071] | 58 | # ..../configure --target=arm-rtems4.11 ... BSP_ZYNQ_RAM_LENGTH=256M |
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[e5d706c] | 59 | # |
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[e9d98071] | 60 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_a9_qemu],[256M]) |
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| 61 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc702],[1024M]) |
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| 62 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc706],[1024M]) |
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| 63 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zedboard],[512M]) |
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| 64 | RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[*],[256M]) |
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| 65 | RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length]) |
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| 66 | |
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[e5d706c] | 67 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], |
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| 68 | [ZYNQ_RAM_ORIGIN="0x00000000" |
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| 69 | ZYNQ_RAM_MMU="0x0fffc000" |
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| 70 | ZYNQ_RAM_MMU_LENGTH="16k" |
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| 71 | ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN}" |
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[e9d98071] | 72 | ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 16k" |
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[e5d706c] | 73 | ZYNQ_RAM_INT_0_ORIGIN="0x00000000" |
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| 74 | ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" |
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| 75 | ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" |
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| 76 | ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) |
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| 77 | |
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| 78 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc702], |
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| 79 | [ZYNQ_RAM_ORIGIN="0x00100000" |
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| 80 | ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" |
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| 81 | ZYNQ_RAM_MMU_LENGTH="16k" |
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| 82 | ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" |
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[e9d98071] | 83 | ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k" |
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[e5d706c] | 84 | ZYNQ_RAM_INT_0_ORIGIN="0x00000000" |
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| 85 | ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" |
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| 86 | ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" |
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| 87 | ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) |
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| 88 | |
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| 89 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc706], |
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| 90 | [ZYNQ_RAM_ORIGIN="0x00400000" |
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| 91 | ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" |
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| 92 | ZYNQ_RAM_MMU_LENGTH="16k" |
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| 93 | ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" |
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[e9d98071] | 94 | ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k" |
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[e5d706c] | 95 | ZYNQ_RAM_INT_0_ORIGIN="0x00000000" |
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| 96 | ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" |
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| 97 | ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" |
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| 98 | ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) |
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| 99 | |
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| 100 | AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zedboard], |
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| 101 | [ZYNQ_RAM_ORIGIN="0x00100000" |
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| 102 | ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" |
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| 103 | ZYNQ_RAM_MMU_LENGTH="16k" |
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| 104 | ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" |
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[e9d98071] | 105 | ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k" |
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[e5d706c] | 106 | ZYNQ_RAM_INT_0_ORIGIN="0x00000000" |
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| 107 | ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" |
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| 108 | ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" |
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| 109 | ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) |
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| 110 | |
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| 111 | AC_DEFUN([ZYNQ_LINKCMD],[ |
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| 112 | AC_ARG_VAR([$1],[$2; default $3])dnl |
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| 113 | [$1]=[$]{[$1]:-[$3]} |
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| 114 | ]) |
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| 115 | |
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| 116 | ZYNQ_LINKCMD([ZYNQ_CPUS],[Number of active cores],[${ZYNQ_CPUS}]) |
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| 117 | ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN],[normal RAM region origin],[${ZYNQ_RAM_ORIGIN}]) |
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[e9d98071] | 118 | ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH],[normal RAM region length],[${BSP_ZYNQ_RAM_LENGTH}]) |
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[e5d706c] | 119 | ZYNQ_LINKCMD([ZYNQ_RAM_MMU],[MMU region origin],[${ZYNQ_RAM_MMU}]) |
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| 120 | ZYNQ_LINKCMD([ZYNQ_RAM_MMU_LENGTH],[MMU region length],[${ZYNQ_RAM_MMU_LENGTH}]) |
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| 121 | ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN_AVAILABLE],[origin of available RAM],[${ZYNQ_RAM_ORIGIN_AVAILABLE}]) |
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| 122 | ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH_AVAILABLE],[length of available RAM],[${ZYNQ_RAM_LENGTH_AVAILABLE}]) |
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| 123 | ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_ORIGIN],[internal 0 RAM region origin],[${ZYNQ_RAM_INT_0_ORIGIN}]) |
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| 124 | ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_LENGTH],[internal 0 RAM region length],[${ZYNQ_RAM_INT_0_LENGTH}]) |
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| 125 | ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_ORIGIN],[internal 1 RAM region origin],[${ZYNQ_RAM_INT_1_ORIGIN}]) |
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| 126 | ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_LENGTH],[internal 1 RAM region length],[${ZYNQ_RAM_INT_1_LENGTH}]) |
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[db42c079] | 127 | |
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[a94d46c8] | 128 | RTEMS_BSP_CLEANUP_OPTIONS(0, 1) |
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| 129 | |
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[e5d706c] | 130 | AC_CONFIG_FILES([ |
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| 131 | Makefile |
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| 132 | startup/linkcmds]) |
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[a94d46c8] | 133 | AC_OUTPUT |
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