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start.S @ 7cc96f5

4.104.114.84.95

Last change on this file since 7cc96f5 was 4564566, checked in by Joel Sherrill <joel.sherrill@…>, on 09/13/00 at 13:45:05

2000-09-13 Emmanuel Raguet <raguet@…>

vegaplus BSP submitted by Emmanuel Raguet <raguet@…> and Eric Valette <valette@…>.
vegaplus/bsp_specs, configure.in, console/Makefile.am, include/Makefile.am, include/bsp.h, include/registers.h, irq/Makefile.am, irq/bsp_irq_asm.S, irq/bsp_irq_init.c, irq/irq.c, irq/irq.h, start/Makefile.am, start/start.S, startup/Makefile.am, startup/bspstart.c, startup/exit.c, startup/linkcmds, wrapup/Makefile.am: New files.

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File size: 6.5 KB

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1	/*
2	* start.S : RTEMS entry point
3	*
4	* Copyright (C) 2000 Canon Research Centre France SA.
5	* Emmanuel Raguet, mailto:raguet@crf.canon.fr
6	*
7	* The license and distribution terms for this file may be
8	* found in found in the file LICENSE in this distribution or at
9	* http://www.OARcorp.com/rtems/license.html.
10	*
11	*/
12
13	/* Register definition */
14
15	.equ CNTL_BASE_ADR, 0xF3000 /* Base address of registers */
16	.equ PORTCNTL, 0x0C60
17	.equ CSCNTL0_0, 0x0C00 /* Offset of CS0CNTL */
18	.equ CSCNTL0_1, 0x0C04 /* Offset of CS0CNTL */
19	.equ CSCNTL0_2, 0x0C08 /* Offset of CS0CNTL */
20	.equ CSCNTL1_0, 0x0C20 /* Offset of CS0CNTL */
21	.equ CSCNTL1_1, 0x0C24 /* Offset of CS0CNTL */
22	.equ CSCNTL1_2, 0x0C28 /* Offset of CS0CNTL */
23	.equ CNTL_CLK_ADR, 0xF2000 /* Base address of registers */
24	.equ CLKCNTL, 0x08F4 /* Offset of CS0CNTL */
25	.equ INTHPAI, 0x0800
26	.equ INTEOI, 0x0808
27	.equ EOI, 0x80
28
29	/* Some standard definitions...*/
30
31	.equ Mode_USR, 0x10
32	.equ Mode_FIQ, 0x11
33	.equ Mode_IRQ, 0x12
34	.equ Mode_SVC, 0x13
35	.equ Mode_ABT, 0x17
36	.equ Mode_ABORT, 0x17
37	.equ Mode_UNDEF, 0x1B
38	.equ Mode_SYS, 0x1F /only available on ARM Arch. v4/
39
40	.equ I_Bit, 0x80
41	.equ F_Bit, 0x40
42
43
44	.equ Mode_SVC_MIRQ, Mode_SVC \| I_Bit \| F_Bit
45	.equ Mode_SVC_UIRQ, Mode_SVC
46	.equ Mode_IRQ_MIRQ, Mode_SVC \| I_Bit \| F_Bit
47
48
49	.equ MARK_STACK, 0 /Fill every stack with a pattern for debug (0 or 1)/
50
51	/*-----------------------------------------------------------------------------
52	* Definitions
53	----------------------------------------------------------------------------*/
54	.equ PID_RAM_Limit, 0x1800
55
56	/* stack size definition */
57	.equ FIQ_StackSize, 0x400 /* FIQ stack size */
58	.equ IRQ_StackSize, 0xE00 /* IRQ stack size */
59	.equ SVC_StackSize, 0x200 /* SVC stack size */
60	.equ ABORT_StackSize, 0x100 /* ABORT stack size */
61	.equ UNDEF_StackSize, 0x100 /* UNDEF stack size */
62
63	/* sack size address */
64	.equ Stack_Limit, PID_RAM_Limit
65	.equ SVC_Stack, Stack_Limit
66	.equ ABORT_Stack, Stack_Limit - SVC_StackSize
67	.equ UNDEF_Stack, ABORT_Stack - ABORT_StackSize
68	.equ IRQ_Stack, UNDEF_Stack - UNDEF_StackSize
69	.equ FIQ_Stack, IRQ_Stack - IRQ_StackSize
70	.equ END_FIQ, FIQ_Stack - FIQ_StackSize
71
72	.text
73	.globl _start
74
75	/*
76	* This "strange" code is used to switch the memory access
77	* from 8 bits to 16 bits, because the vega plus accesses
78	* the memory via 8 bits at reset time
79	*/
80
81	_start:
82	.long 0x00300010 /LDR r3,0x18/
83	.long 0x00E5009F
84
85	.long 0x00400010
86	.long 0x00E5009F
87
88	.long 0x004600B0
89	.long 0x00E100C3
90
91	.long 0x00400002 /* CS0 = 16 bits*/
92	.long 0x00E300A0
93
94	.long 0x004200B0
95	.long 0x00E100C3
96
97	.long 0x00000009
98	.long 0x00EA0000
99
100	.long 0x003C0000
101	.long 0x0000000F
102
103	.long 0x00A60087
104	.long 0x00000000
105
106	.code 32
107
108	/* --- Initialise external bus*/
109	Real_start:
110	MOV r0,#CNTL_BASE_ADR
111
112	/Load timing configuration of CS0/
113	LDR r1, =0x0804
114	STR r1, [r0,#CSCNTL0_0]
115	LDR r1, =0xC432
116	STR r1, [r0,#CSCNTL1_0]
117
118	/* Load timing configuration and access mode of CS1
119	NOTE : Important for macro REGION_INIT of Region_init.s
120	if initialisation of data in external RAM */
121	LDR r1, =0x2200
122	STR r1, [r0,#CSCNTL0_1]
123	LDR r1, =0x8022
124	STR r1, [r0,#CSCNTL1_1]
125
126	/* Load timing configuration and access mode of CS2 */
127	LDR r1, =0x342
128	STR r1, [r0,#CSCNTL0_2]
129	LDR r1, =0xA2
130	STR r1, [r0,#CSCNTL1_2]
131
132
133	MOV r0,#CNTL_CLK_ADR
134	/* Load clock mode 55 MHz */
135	LDR r1, =0x0010
136	STR r1, [r0,#CLKCNTL]
137
138	/* Copy data from FLASH to RAM */
139	LDR r0, =_initdata /* load address of region */
140	LDR r1, =0x400000 /* execution address of region */
141	LDR r2, =_edata /* copy execution address into r2 */
142
143	copy:
144	CMP r1, r2 /* loop whilst r1 < r2 */
145	LDRLO r3, [r0], #4
146	STRLO r3, [r1], #4
147	BLO copy
148
149	/* zero the bss */
150	LDR r1, =__bss_end__ /* get end of ZI region */
151	LDR r0, =__bss_start__ /* load base address of ZI region */
152	zi_init:
153	MOV r2, #0
154	CMP r0, r1 /* loop whilst r0 < r1 */
155	STRLOT r2, [r0], #4
156	BLO zi_init
157
158
159	/* Load basic ARM7 interrupt table */
160	VectorInit:
161	MOV R8, #0
162	ADR R9, Vector_Init_Block
163	LDMIA R9!, {R0-R7} /* Copy the Vectors (8 words) */
164	STMIA R8!, {R0-R7}
165	LDMIA R9!, {R0-R7} /* Copy the .long'ed addresses (8 words) */
166	STMIA R8!, {R0-R7}
167
168	B init2
169
170	/*******************************************************
171	standard exception vectors table
172	*** Must be located at address 0
173	********************************************************/
174
175	Vector_Init_Block:
176	LDR PC, Reset_Addr
177	LDR PC, Undefined_Addr
178	LDR PC, SWI_Addr
179	LDR PC, Prefetch_Addr
180	LDR PC, Abort_Addr
181	NOP
182	LDR PC, IRQ_Addr
183	LDR PC, FIQ_Addr
184
185	.globl Reset_Addr
186	Reset_Addr: .long _start
187	Undefined_Addr: .long Undefined_Handler
188	SWI_Addr: .long SWI_Handler
189	Prefetch_Addr: .long Prefetch_Handler
190	Abort_Addr: .long Abort_Handler
191	.long 0
192	IRQ_Addr: .long IRQ_Handler
193	FIQ_Addr: .long FIQ_Handler
194
195	/* The following handlers do not do anything useful */
196	.globl Undefined_Handler
197	Undefined_Handler:
198	B Undefined_Handler
199	.globl SWI_Handler
200	SWI_Handler:
201	B SWI_Handler
202	.globl Prefetch_Handler
203	Prefetch_Handler:
204	B Prefetch_Handler
205	.globl Abort_Handler
206	Abort_Handler:
207	B Abort_Handler
208	.globl IRQ_Handler
209	IRQ_Handler:
210	B IRQ_Handler
211	.globl FIQ_Handler
212	FIQ_Handler:
213	B FIQ_Handler
214
215	init2 :
216	/* --- Initialise stack pointer registers
217	Set up the ABORT stack pointer last and stay in SVC mode */
218	MOV r0, #(Mode_ABORT \| I_Bit \| F_Bit) /* No interrupts */
219	MSR cpsr, r0
220	LDR sp, =ABORT_Stack
221
222	/* Enter IRQ mode and set up the IRQ stack pointer */
223	MOV r0, #Mode_IRQ \| I_Bit \| F_Bit /* No interrupts */
224	MSR cpsr, r0
225	LDR sp, =IRQ_Stack
226
227	/* Enter FIQ mode and set up the FIQ stack pointer */
228	MOV r0, #Mode_FIQ \| I_Bit \| F_Bit /* No interrupts */
229	MSR cpsr, r0
230	LDR sp, =FIQ_Stack
231
232	/* Set up the SVC stack pointer last and stay in SVC mode */
233	MOV r0, #Mode_SVC \| I_Bit \| F_Bit /* No interrupts */
234	MSR cpsr, r0
235	LDR sp, =SVC_Stack
236
237	/* --- Now we enter the C code */
238
239	B boot_card
240
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