1 | /* |
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2 | * start.S : RTEMS entry point |
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3 | * |
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4 | * Copyright (C) 2000 Canon Research Centre France SA. |
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5 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in found in the file LICENSE in this distribution or at |
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9 | * http://www.OARcorp.com/rtems/license.html. |
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10 | * |
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11 | */ |
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12 | |
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13 | /* Register definition */ |
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14 | |
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15 | .equ CNTL_BASE_ADR, 0xF3000 /* Base address of registers */ |
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16 | .equ PORTCNTL, 0x0C60 |
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17 | .equ CSCNTL0_0, 0x0C00 /* Offset of CS0CNTL */ |
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18 | .equ CSCNTL0_1, 0x0C04 /* Offset of CS0CNTL */ |
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19 | .equ CSCNTL0_2, 0x0C08 /* Offset of CS0CNTL */ |
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20 | .equ CSCNTL1_0, 0x0C20 /* Offset of CS0CNTL */ |
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21 | .equ CSCNTL1_1, 0x0C24 /* Offset of CS0CNTL */ |
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22 | .equ CSCNTL1_2, 0x0C28 /* Offset of CS0CNTL */ |
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23 | .equ CNTL_CLK_ADR, 0xF2000 /* Base address of registers */ |
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24 | .equ CLKCNTL, 0x08F4 /* Offset of CS0CNTL */ |
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25 | .equ INTHPAI, 0x0800 |
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26 | .equ INTEOI, 0x0808 |
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27 | .equ EOI, 0x80 |
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28 | |
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29 | /* Some standard definitions...*/ |
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30 | |
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31 | .equ Mode_USR, 0x10 |
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32 | .equ Mode_FIQ, 0x11 |
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33 | .equ Mode_IRQ, 0x12 |
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34 | .equ Mode_SVC, 0x13 |
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35 | .equ Mode_ABT, 0x17 |
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36 | .equ Mode_ABORT, 0x17 |
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37 | .equ Mode_UNDEF, 0x1B |
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38 | .equ Mode_SYS, 0x1F /*only available on ARM Arch. v4*/ |
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39 | |
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40 | .equ I_Bit, 0x80 |
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41 | .equ F_Bit, 0x40 |
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42 | |
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43 | |
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44 | .equ Mode_SVC_MIRQ, Mode_SVC | I_Bit | F_Bit |
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45 | .equ Mode_SVC_UIRQ, Mode_SVC |
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46 | .equ Mode_IRQ_MIRQ, Mode_SVC | I_Bit | F_Bit |
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47 | |
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48 | |
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49 | .equ MARK_STACK, 0 /*Fill every stack with a pattern for debug (0 or 1)*/ |
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50 | |
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51 | /*----------------------------------------------------------------------------- |
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52 | * Definitions |
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53 | ----------------------------------------------------------------------------*/ |
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54 | .equ PID_RAM_Limit, 0x1800 |
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55 | |
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56 | /* stack size definition */ |
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57 | .equ FIQ_StackSize, 0x400 /* FIQ stack size */ |
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58 | .equ IRQ_StackSize, 0xE00 /* IRQ stack size */ |
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59 | .equ SVC_StackSize, 0x200 /* SVC stack size */ |
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60 | .equ ABORT_StackSize, 0x100 /* ABORT stack size */ |
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61 | .equ UNDEF_StackSize, 0x100 /* UNDEF stack size */ |
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62 | |
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63 | /* sack size address */ |
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64 | .equ Stack_Limit, PID_RAM_Limit |
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65 | .equ SVC_Stack, Stack_Limit |
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66 | .equ ABORT_Stack, Stack_Limit - SVC_StackSize |
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67 | .equ UNDEF_Stack, ABORT_Stack - ABORT_StackSize |
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68 | .equ IRQ_Stack, UNDEF_Stack - UNDEF_StackSize |
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69 | .equ FIQ_Stack, IRQ_Stack - IRQ_StackSize |
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70 | .equ END_FIQ, FIQ_Stack - FIQ_StackSize |
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71 | |
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72 | .text |
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73 | .globl _start |
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74 | |
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75 | /* |
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76 | * This "strange" code is used to switch the memory access |
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77 | * from 8 bits to 16 bits, because the vega plus accesses |
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78 | * the memory via 8 bits at reset time |
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79 | */ |
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80 | |
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81 | _start: |
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82 | .long 0x00300010 /*LDR r3,0x18*/ |
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83 | .long 0x00E5009F |
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84 | |
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85 | .long 0x00400010 |
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86 | .long 0x00E5009F |
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87 | |
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88 | .long 0x004600B0 |
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89 | .long 0x00E100C3 |
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90 | |
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91 | .long 0x00400002 /* CS0 = 16 bits*/ |
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92 | .long 0x00E300A0 |
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93 | |
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94 | .long 0x004200B0 |
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95 | .long 0x00E100C3 |
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96 | |
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97 | .long 0x00000009 |
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98 | .long 0x00EA0000 |
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99 | |
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100 | .long 0x003C0000 |
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101 | .long 0x0000000F |
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102 | |
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103 | .long 0x00A60087 |
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104 | .long 0x00000000 |
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105 | |
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106 | .code 32 |
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107 | |
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108 | /* --- Initialise external bus*/ |
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109 | Real_start: |
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110 | MOV r0,#CNTL_BASE_ADR |
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111 | |
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112 | /*Load timing configuration of CS0*/ |
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113 | LDR r1, =0x0804 |
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114 | STR r1, [r0,#CSCNTL0_0] |
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115 | LDR r1, =0xC432 |
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116 | STR r1, [r0,#CSCNTL1_0] |
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117 | |
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118 | /* Load timing configuration and access mode of CS1 |
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119 | NOTE : Important for macro REGION_INIT of Region_init.s |
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120 | if initialisation of data in external RAM */ |
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121 | LDR r1, =0x2200 |
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122 | STR r1, [r0,#CSCNTL0_1] |
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123 | LDR r1, =0x8022 |
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124 | STR r1, [r0,#CSCNTL1_1] |
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125 | |
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126 | /* Load timing configuration and access mode of CS2 */ |
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127 | LDR r1, =0x342 |
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128 | STR r1, [r0,#CSCNTL0_2] |
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129 | LDR r1, =0xA2 |
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130 | STR r1, [r0,#CSCNTL1_2] |
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131 | |
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132 | |
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133 | MOV r0,#CNTL_CLK_ADR |
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134 | /* Load clock mode 55 MHz */ |
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135 | LDR r1, =0x0010 |
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136 | STR r1, [r0,#CLKCNTL] |
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137 | |
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138 | /* Copy data from FLASH to RAM */ |
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139 | LDR r0, =_initdata /* load address of region */ |
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140 | LDR r1, =0x400000 /* execution address of region */ |
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141 | LDR r2, =_edata /* copy execution address into r2 */ |
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142 | |
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143 | copy: |
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144 | CMP r1, r2 /* loop whilst r1 < r2 */ |
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145 | LDRLO r3, [r0], #4 |
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146 | STRLO r3, [r1], #4 |
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147 | BLO copy |
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148 | |
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149 | /* zero the bss */ |
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150 | LDR r1, =__bss_end__ /* get end of ZI region */ |
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151 | LDR r0, =__bss_start__ /* load base address of ZI region */ |
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152 | zi_init: |
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153 | MOV r2, #0 |
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154 | CMP r0, r1 /* loop whilst r0 < r1 */ |
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155 | STRLOT r2, [r0], #4 |
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156 | BLO zi_init |
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157 | |
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158 | |
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159 | /* Load basic ARM7 interrupt table */ |
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160 | VectorInit: |
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161 | MOV R8, #0 |
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162 | ADR R9, Vector_Init_Block |
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163 | LDMIA R9!, {R0-R7} /* Copy the Vectors (8 words) */ |
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164 | STMIA R8!, {R0-R7} |
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165 | LDMIA R9!, {R0-R7} /* Copy the .long'ed addresses (8 words) */ |
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166 | STMIA R8!, {R0-R7} |
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167 | |
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168 | B init2 |
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169 | |
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170 | /******************************************************* |
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171 | standard exception vectors table |
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172 | *** Must be located at address 0 |
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173 | ********************************************************/ |
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174 | |
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175 | Vector_Init_Block: |
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176 | LDR PC, Reset_Addr |
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177 | LDR PC, Undefined_Addr |
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178 | LDR PC, SWI_Addr |
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179 | LDR PC, Prefetch_Addr |
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180 | LDR PC, Abort_Addr |
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181 | NOP |
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182 | LDR PC, IRQ_Addr |
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183 | LDR PC, FIQ_Addr |
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184 | |
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185 | .globl Reset_Addr |
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186 | Reset_Addr: .long _start |
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187 | Undefined_Addr: .long Undefined_Handler |
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188 | SWI_Addr: .long SWI_Handler |
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189 | Prefetch_Addr: .long Prefetch_Handler |
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190 | Abort_Addr: .long Abort_Handler |
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191 | .long 0 |
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192 | IRQ_Addr: .long IRQ_Handler |
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193 | FIQ_Addr: .long FIQ_Handler |
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194 | |
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195 | /* The following handlers do not do anything useful */ |
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196 | .globl Undefined_Handler |
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197 | Undefined_Handler: |
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198 | B Undefined_Handler |
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199 | .globl SWI_Handler |
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200 | SWI_Handler: |
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201 | B SWI_Handler |
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202 | .globl Prefetch_Handler |
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203 | Prefetch_Handler: |
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204 | B Prefetch_Handler |
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205 | .globl Abort_Handler |
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206 | Abort_Handler: |
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207 | B Abort_Handler |
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208 | .globl IRQ_Handler |
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209 | IRQ_Handler: |
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210 | B IRQ_Handler |
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211 | .globl FIQ_Handler |
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212 | FIQ_Handler: |
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213 | B FIQ_Handler |
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214 | |
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215 | init2 : |
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216 | /* --- Initialise stack pointer registers |
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217 | Set up the ABORT stack pointer last and stay in SVC mode */ |
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218 | MOV r0, #(Mode_ABORT | I_Bit | F_Bit) /* No interrupts */ |
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219 | MSR cpsr, r0 |
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220 | LDR sp, =ABORT_Stack |
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221 | |
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222 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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223 | MOV r0, #Mode_IRQ | I_Bit | F_Bit /* No interrupts */ |
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224 | MSR cpsr, r0 |
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225 | LDR sp, =IRQ_Stack |
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226 | |
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227 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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228 | MOV r0, #Mode_FIQ | I_Bit | F_Bit /* No interrupts */ |
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229 | MSR cpsr, r0 |
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230 | LDR sp, =FIQ_Stack |
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231 | |
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232 | /* Set up the SVC stack pointer last and stay in SVC mode */ |
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233 | MOV r0, #Mode_SVC | I_Bit | F_Bit /* No interrupts */ |
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234 | MSR cpsr, r0 |
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235 | LDR sp, =SVC_Stack |
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236 | |
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237 | /* --- Now we enter the C code */ |
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238 | |
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239 | B boot_card |
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240 | |
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241 | |
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242 | |
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243 | |
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244 | |
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245 | |
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246 | |
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248 | |
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249 | |
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250 | |
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251 | |
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