| 1 | /* |
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| 2 | * VEGA PLUS registers declaration |
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| 3 | * |
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| 4 | * Copyright (c) 2000 Canon Research France SA. |
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| 5 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in found in the file LICENSE in this distribution or at |
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| 9 | * http://www.rtems.com/license/LICENSE. |
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| 10 | * |
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| 11 | */ |
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| 12 | |
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| 13 | #ifndef __LMREGS_H__ |
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| 14 | #define __LMREGS_H__ |
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| 15 | |
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| 16 | /* |
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| 17 | * VARIABLE DECLARATION |
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| 18 | ****************************************************************************** |
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| 19 | */ |
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| 20 | |
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| 21 | /* register area size */ |
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| 22 | #define LM_REG_AREA_SIZ (0x4000/4) |
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| 23 | |
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| 24 | /*** Register mapping : defined by indexes in an array ***/ |
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| 25 | /*** NOTE : only 1 register every 4 byte address location (+ some holes) */ |
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| 26 | #ifndef __asm__ |
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| 27 | extern volatile unsigned long *Regs; /* Chip registers */ |
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| 28 | #endif |
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| 29 | |
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| 30 | /****************************************************************************** |
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| 31 | * RADIO CONTROLLER BLOCK 0x0C00 - 0x0FFF * |
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| 32 | ****************************************************************************** |
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| 33 | */ |
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| 34 | |
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| 35 | #define RC_BASE 0xC00 |
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| 36 | |
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| 37 | #define RCCNTL ((RC_BASE+0x00)/4) |
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| 38 | #define RCIOCNTL0 ((RC_BASE+0x04)/4) |
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| 39 | #define RCIOCNTL1 ((RC_BASE+0x08)/4) |
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| 40 | #define SYNTCNTL0 ((RC_BASE+0x0C)/4) |
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| 41 | #define SYNTCNTL1 ((RC_BASE+0x10)/4) |
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| 42 | #define SYNTCNTL2 ((RC_BASE+0x14)/4) |
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| 43 | #define SYNTFCNTL ((RC_BASE+0x18)/4) |
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| 44 | #define SYNTPCNTL ((RC_BASE+0x1C)/4) |
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| 45 | #define RSSICNTL ((RC_BASE+0x20)/4) |
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| 46 | #define RSSIBASEL ((RC_BASE+0x24)/4) |
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| 47 | #define RSSIBASEH ((RC_BASE+0x28)/4) |
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| 48 | #define CURRSSI ((RC_BASE+0x2C)/4) |
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| 49 | #define RFSCAN ((RC_BASE+0x30)/4) |
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| 50 | #define CURRF ((RC_BASE+0x34)/4) |
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| 51 | #define CURRSSIA ((RC_BASE+0x38)/4) |
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| 52 | #define CURRSSIB ((RC_BASE+0x3C)/4) |
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| 53 | #define CURRSSIAB ((RC_BASE+0x40)/4) |
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| 54 | #define ADCDATAL ((RC_BASE+0x44)/4) |
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| 55 | #define ADCDATAH ((RC_BASE+0x48)/4) |
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| 56 | #define SLICECNTL ((RC_BASE+0x4C)/4) |
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| 57 | #define RCIOCNTL2 ((RC_BASE+0x50)/4) |
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| 58 | #define RCIOCNTL3 ((RC_BASE+0x54)/4) |
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| 59 | #define ADCREF1L ((RC_BASE+0x58)/4) |
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| 60 | #define ADCREF1H ((RC_BASE+0x5C)/4) |
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| 61 | #define ADCREF2L ((RC_BASE+0x60)/4) |
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| 62 | #define ADCREF2H ((RC_BASE+0x64)/4) |
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| 63 | #define ADCCNTL1 ((RC_BASE+0x68)/4) |
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| 64 | #define ADCCNTL2 ((RC_BASE+0x6C)/4) |
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| 65 | #define TESTREG ((RC_BASE+0x70)/4) |
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| 66 | #define SYNTLCNTL ((RC_BASE+0x74)/4) |
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| 67 | #define SYNTCNTL3 ((RC_BASE+0x78)/4) |
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| 68 | #define ADCPERIOD ((RC_BASE+0x7C)/4) |
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| 69 | #define SYNTIOCNTL ((RC_BASE+0x80)/4) /* added 30/08/99 */ |
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| 70 | |
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| 71 | /* modified 30/08/99 by LHT */ |
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| 72 | #define SHAPE0 ((RC_BASE+0x100)/4) /* previously 0x80 */ |
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| 73 | #define SHAPE1 ((RC_BASE+0x104)/4) |
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| 74 | #define SHAPE2 ((RC_BASE+0x108)/4) |
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| 75 | #define SHAPE3 ((RC_BASE+0x10C)/4) |
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| 76 | #define SHAPE4 ((RC_BASE+0x110)/4) |
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| 77 | #define SHAPE5 ((RC_BASE+0x114)/4) |
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| 78 | #define SHAPE6 ((RC_BASE+0x118)/4) |
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| 79 | #define SHAPE7 ((RC_BASE+0x11C)/4) |
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| 80 | #define SHAPE8 ((RC_BASE+0x120)/4) |
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| 81 | #define SHAPE9 ((RC_BASE+0x124)/4) |
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| 82 | #define SHAPE10 ((RC_BASE+0x128)/4) |
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| 83 | #define SHAPE11 ((RC_BASE+0x12C)/4) |
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| 84 | #define SHAPE12 ((RC_BASE+0x130)/4) |
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| 85 | #define SHAPERMID ((RC_BASE+0x134)/4) |
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| 86 | #define SHAPERCNTL ((RC_BASE+0x138)/4) |
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| 87 | #define CURSHAPE ((RC_BASE+0x13C)/4) |
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| 88 | |
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| 89 | /** PLP BLOCK 0x1400 - 0x17FF */ |
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| 90 | |
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| 91 | #define PLP_BASE 0x1400 |
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| 92 | #define DCNTL0 ((PLP_BASE+0x00)/4) |
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| 93 | #define DCNTL1 ((PLP_BASE+0x04)/4) |
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| 94 | #define SYNC0 ((PLP_BASE+0x08)/4) |
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| 95 | #define SYNC1 ((PLP_BASE+0x0C)/4) |
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| 96 | #define RXSTARTDL ((PLP_BASE+0x10)/4) |
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| 97 | #define TXSTARTDL ((PLP_BASE+0x14)/4) |
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| 98 | #define RXSTOPDL ((PLP_BASE+0x1C)/4) |
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| 99 | #define RXSYNCT ((PLP_BASE+0x20)/4) |
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| 100 | #define HALF_TXSLOT ((PLP_BASE+0x24)/4) |
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| 101 | #define SCB_NUMBER ((PLP_BASE+0x28)/4) |
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| 102 | #define SCB_OPPNUMBER ((PLP_BASE+0x2C)/4) |
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| 103 | #define TXFRAME ((PLP_BASE+0x40)/4) |
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| 104 | #define MSLTPTR ((PLP_BASE+0x44)/4) |
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| 105 | #define CLOCK_CORR ((PLP_BASE+0x48)/4) |
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| 106 | #define PRESYNC ((PLP_BASE+0x4C)/4) |
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| 107 | #define PLPFINE ((PLP_BASE+0x50)/4) |
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| 108 | #define PLPINDEL ((PLP_BASE+0x54)/4) |
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| 109 | #define TXRXSKW ((PLP_BASE+0x58)/4) |
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| 110 | #define PLPALIN ((PLP_BASE+0x5C)/4) |
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| 111 | #define SUSPRFCNTL ((PLP_BASE+0x60)/4) |
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| 112 | #define SUSPCNTL ((PLP_BASE+0x64)/4) |
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| 113 | #define SUSPFC ((PLP_BASE+0x68)/4) |
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| 114 | #define TSTCNTL ((PLP_BASE+0x6C)/4) |
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| 115 | #define TSTDST ((PLP_BASE+0x70)/4) |
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| 116 | #define TSTTXD ((PLP_BASE+0x74)/4) |
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| 117 | #define TSTRXD ((PLP_BASE+0x78)/4) |
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| 118 | #define PLPID ((PLP_BASE+0x7C)/4) |
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| 119 | |
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| 120 | /** ENCRYPTION ENGINE 0x1800 - 0x1BFF */ |
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| 121 | |
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| 122 | #define EE_BASE 0x1800 |
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| 123 | #define EECNTL ((EE_BASE+0x00)/4) |
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| 124 | #define EEBASEL ((EE_BASE+0x08)/4) |
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| 125 | #define EEBASEH ((EE_BASE+0x0C)/4) |
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| 126 | #define MFL ((EE_BASE+0x10)/4) |
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| 127 | #define MFM ((EE_BASE+0x14)/4) |
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| 128 | #define MFH ((EE_BASE+0x18)/4) |
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| 129 | |
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| 130 | /** TELEPHONE ANSWERING DEVICE 0x1C00 - 0x1FFF */ |
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| 131 | |
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| 132 | #define TAD_BASE 0x1C00 |
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| 133 | #define TADCNTL ((TAD_BASE+0x00)/4) |
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| 134 | #define TADCODE1 ((TAD_BASE+0x04)/4) |
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| 135 | #define TADCODE2 ((TAD_BASE+0x08)/4) |
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| 136 | #define TADCODE3 ((TAD_BASE+0x0C)/4) |
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| 137 | #define TADSTAT ((TAD_BASE+0x10)/4) |
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| 138 | #define TADADDRL ((TAD_BASE+0x14)/4) |
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| 139 | #define TADADDRM ((TAD_BASE+0x18)/4) |
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| 140 | #define TADADDRH ((TAD_BASE+0x1C)/4) |
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| 141 | #define TADLEN ((TAD_BASE+0x20)/4) |
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| 142 | #define TADAUXDAT1 ((TAD_BASE+0x24)/4) |
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| 143 | #define TADAUXDAT2 ((TAD_BASE+0x28)/4) |
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| 144 | #define TADSHMEML ((TAD_BASE+0x2C)/4) |
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| 145 | #define TADSHMEMH ((TAD_BASE+0x30)/4) |
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| 146 | #define TADCMD ((TAD_BASE+0x34)/4) |
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| 147 | |
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| 148 | /** VOICE INTERFACE BLOCK 0x2000 - 0x23FF */ |
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| 149 | |
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| 150 | #define PAINT_BASE 0x2000 |
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| 151 | #define PAINTCNTL ((PAINT_BASE+0x00)/4) |
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| 152 | #define PAINTPLLCNTL ((PAINT_BASE+0x08)/4) |
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| 153 | #define PAINTPLLSTAT ((PAINT_BASE+0x0C)/4) |
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| 154 | #define VBAFECNTL ((PAINT_BASE+0x10)/4) |
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| 155 | #define VBAFEAMP ((PAINT_BASE+0x14)/4) |
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| 156 | #define VBAFEPREAMP ((PAINT_BASE+0x18)/4) |
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| 157 | #define PCMAUX ((PAINT_BASE+0x1C)/4) |
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| 158 | #define PCM0RX ((PAINT_BASE+0x20)/4) |
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| 159 | #define PCM0TX ((PAINT_BASE+0x24)/4) |
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| 160 | #define PCM1RX ((PAINT_BASE+0x28)/4) |
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| 161 | #define PCM1TX ((PAINT_BASE+0x2C)/4) |
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| 162 | #define ADPCM0RX ((PAINT_BASE+0x30)/4) |
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| 163 | #define ADPCM0TX ((PAINT_BASE+0x34)/4) |
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| 164 | #define ADPCM1RX ((PAINT_BASE+0x38)/4) |
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| 165 | #define ADPCM1TX ((PAINT_BASE+0x3C)/4) |
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| 166 | #define MPDCNTL ((PAINT_BASE+0x40)/4) |
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| 167 | #define MPDREADY ((PAINT_BASE+0x44)/4) |
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| 168 | #define MPDABS ((PAINT_BASE+0x48)/4) |
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| 169 | #define MPDS1 ((PAINT_BASE+0x4C)/4) |
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| 170 | #define MPDS2 ((PAINT_BASE+0x50)/4) |
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| 171 | #define HPPCMCNTL ((PAINT_BASE+0x60)/4) |
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| 172 | #define HPOUT ((PAINT_BASE+0x64)/4) |
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| 173 | #define HPIN ((PAINT_BASE+0x68)/4) |
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| 174 | #define PAINTBASE0 ((PAINT_BASE+0x70)/4) |
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| 175 | #define PAINTBASE1 ((PAINT_BASE+0x74)/4) |
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| 176 | #define G726AI0 ((PAINT_BASE+0x80)/4) |
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| 177 | #define G726AI1 ((PAINT_BASE+0x84)/4) |
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| 178 | #define G726GAIN0 ((PAINT_BASE+0x88)/4) |
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| 179 | #define G726GAIN1 ((PAINT_BASE+0x8C)/4) |
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| 180 | #define G726VOL ((PAINT_BASE+0x90)/4) |
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| 181 | #define G726GST ((PAINT_BASE+0x94)/4) |
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| 182 | #define G726CNTL0 ((PAINT_BASE+0x98)/4) |
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| 183 | #define G726CNTL1 ((PAINT_BASE+0x9C)/4) |
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| 184 | #define G726CHANNEL ((PAINT_BASE+0xA0)/4) |
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| 185 | #define G726CHANENB ((PAINT_BASE+0xA4)/4) |
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| 186 | |
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| 187 | /** GENERAL REGISTERS BLOCK 0x2800 - 0x2CFF */ |
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| 188 | |
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| 189 | #define MISC_BASE 0x2800 |
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| 190 | #define CHIPID ((MISC_BASE+0x00)/4) |
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| 191 | #define DEVICEID ((MISC_BASE+0x04)/4) |
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| 192 | #define IOACNTL ((MISC_BASE+0x10)/4) |
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| 193 | #define IOADATA ((MISC_BASE+0x18)/4) |
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| 194 | #define IOBCNTL ((MISC_BASE+0x20)/4) |
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| 195 | #define IOBDATA ((MISC_BASE+0x28)/4) |
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| 196 | #define IOCCNTL1 ((MISC_BASE+0x30)/4) |
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| 197 | #define IOCCNTL2 ((MISC_BASE+0x34)/4) |
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| 198 | #define IOCDATA ((MISC_BASE+0x38)/4) |
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| 199 | #define IODCNTL1 ((MISC_BASE+0x40)/4) |
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| 200 | #define IODCNTL2 ((MISC_BASE+0x44)/4) |
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| 201 | #define IODDATA ((MISC_BASE+0x48)/4) |
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| 202 | #define IOECNTL1 ((MISC_BASE+0x50)/4) |
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| 203 | #define IOECNTL2 ((MISC_BASE+0x54)/4) |
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| 204 | #define IOEDATA ((MISC_BASE+0x58)/4) |
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| 205 | #define IOFCNTL ((MISC_BASE+0x60)/4) |
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| 206 | #define IOFDATA ((MISC_BASE+0x68)/4) |
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| 207 | #define IOGCNTL ((MISC_BASE+0x70)/4) |
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| 208 | #define IOGDATA ((MISC_BASE+0x78)/4) |
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| 209 | #define IOHCNTL ((MISC_BASE+0x80)/4) |
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| 210 | #define IOHDATA ((MISC_BASE+0x88)/4) |
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| 211 | #define RINGCNTL ((MISC_BASE+0x90)/4) |
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| 212 | #define RINGFREQ ((MISC_BASE+0x94)/4) |
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| 213 | #define RSCNTL ((MISC_BASE+0xA0)/4) |
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| 214 | /*#ifndef PRODUCT_VERSION*/ |
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| 215 | #define RSRXD ((MISC_BASE+0xA4)/4) |
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| 216 | #define RSTXD ((MISC_BASE+0xA8)/4) |
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| 217 | /*#endif*/ |
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| 218 | #define PWMCNTL ((MISC_BASE+0xB0)/4) |
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| 219 | #define PWMTIMER0 ((MISC_BASE+0xB4)/4) |
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| 220 | #define PWMTIMER1 ((MISC_BASE+0xB8)/4) |
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| 221 | #define LCDEECNTL1 ((MISC_BASE+0xC0)/4) |
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| 222 | #define LCDEECNTL2 ((MISC_BASE+0xC4)/4) |
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| 223 | #define LCDEEDAIN ((MISC_BASE+0xC8)/4) |
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| 224 | #define LCDEEDAOUT ((MISC_BASE+0xCC)/4) |
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| 225 | #define KEYROW ((MISC_BASE+0xE0)/4) |
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| 226 | #define KEYCOL ((MISC_BASE+0xE4)/4) |
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| 227 | #define KEYDEBOUNCE ((MISC_BASE+0xE8)/4) |
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| 228 | #define DIAGCNTL1 ((MISC_BASE+0xEC)/4) |
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| 229 | #define DIAGCNTL2 ((MISC_BASE+0xF0)/4) |
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| 230 | #define CLKCNTL ((MISC_BASE+0xF4)/4) |
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| 231 | #define OSCCOR ((MISC_BASE+0xF8)/4) |
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| 232 | |
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| 233 | /* PRODUCT_VERSION */ |
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| 234 | /* Added 30/08/99 : New Control register for UART control */ |
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| 235 | #define UART_BASE 0x3000 |
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| 236 | #define RSRBR ((UART_BASE+0x00)/4) |
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| 237 | #define RSTHR ((UART_BASE+0x00)/4) |
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| 238 | #define RSIER ((UART_BASE+0x04)/4) |
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| 239 | #define RSIIR ((UART_BASE+0x08)/4) |
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| 240 | #define RSFCR ((UART_BASE+0x08)/4) |
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| 241 | #define RSLCR ((UART_BASE+0x0C)/4) |
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| 242 | #define RSLSR ((UART_BASE+0x14)/4) |
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| 243 | #define RSDLL ((UART_BASE+0x00)/4) |
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| 244 | #define RSDLH ((UART_BASE+0x04)/4) |
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| 245 | #define RSCNT ((UART_BASE+0x20)/4) |
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| 246 | /*PRODUCT_VERSION*/ |
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| 247 | |
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| 248 | /** THUMB and INTERFACES BLOCK 0x3400 - 0x4FFF */ |
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| 249 | |
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| 250 | #define TIM_BASE 0x3400 |
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| 251 | #define WDCNTL ((TIM_BASE+0x00)/4) |
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| 252 | #define TIMERLOAD0 ((TIM_BASE+0x80)/4) |
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| 253 | #define TIMER0 ((TIM_BASE+0x8C)/4) |
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| 254 | #define TIMERCNTL0 ((TIM_BASE+0x98)/4) |
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| 255 | #define TIMERLOAD1 ((TIM_BASE+0xA0)/4) |
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| 256 | #define TIMER1 ((TIM_BASE+0xAC)/4) |
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| 257 | #define TIMERCNTL1 ((TIM_BASE+0xB8)/4) |
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| 258 | |
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| 259 | #define INTC_BASE 0x3800 |
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| 260 | #define INTMASK ((INTC_BASE+0x20)/4) |
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| 261 | #define INTSTAT ((INTC_BASE+0x24)/4) |
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| 262 | #define INTACK ((INTC_BASE+0x24)/4) |
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| 263 | #define INTACK2 ((INTC_BASE+0x24)) |
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| 264 | #define INTIS ((INTC_BASE+0x28)/4) |
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| 265 | #define INTIS2 ((INTC_BASE+0x28)) |
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| 266 | #define INTHPAI ((INTC_BASE+0x00)/4) |
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| 267 | #define INTHPAI2 ((INTC_BASE+0x00)) |
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| 268 | #define INTLEVEL ((INTC_BASE+0x04)/4) |
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| 269 | #define INTEOI ((INTC_BASE+0x08)/4) |
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| 270 | #define INTEOI2 ((INTC_BASE+0x08)) |
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| 271 | #define INTMASKALL ((INTC_BASE+0x0C)/4) |
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| 272 | #define INTTAB ((INTC_BASE+0x10)/4) |
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| 273 | #define INTCNTL0 ((INTC_BASE+0x80)/4) |
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| 274 | #define INTCNTL1 ((INTC_BASE+0x84)/4) |
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| 275 | #define INTCNTL2 ((INTC_BASE+0x88)/4) |
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| 276 | #define INTCNTL3 ((INTC_BASE+0x8C)/4) |
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| 277 | #define INTCNTL4 ((INTC_BASE+0x90)/4) |
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| 278 | #define INTCNTL5 ((INTC_BASE+0x94)/4) |
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| 279 | #define INTCNTL6 ((INTC_BASE+0x98)/4) |
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| 280 | #define INTCNTL7 ((INTC_BASE+0x9C)/4) |
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| 281 | #define INTCNTL8 ((INTC_BASE+0xA0)/4) |
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| 282 | #define INTCNTL9 ((INTC_BASE+0xA4)/4) |
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| 283 | #define INTCNTL10 ((INTC_BASE+0xA8)/4) |
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| 284 | #define INTCNTL11 ((INTC_BASE+0xAC)/4) |
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| 285 | #define INTCNTL12 ((INTC_BASE+0xB0)/4) |
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| 286 | #define INTCNTL13 ((INTC_BASE+0xB4)/4) |
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| 287 | #define INTCNTL14 ((INTC_BASE+0xB8)/4) |
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| 288 | #define INTCNTL15 ((INTC_BASE+0xBC)/4) |
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| 289 | #define INTGCNTL ((INTC_BASE+0x7C)/4) |
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| 290 | |
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| 291 | /* these "define" are used for the asm code of int managment */ |
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| 292 | #define INTPHAI3 0xF3800 |
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| 293 | #define INTSTAT3 0xF3824 |
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| 294 | #define INTIS3 0xF3828 |
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| 295 | #define INTACK3 0xF3824 |
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| 296 | #define INTEOI3 0xF3808 |
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| 297 | |
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| 298 | #define TI_BASE 0x3C00 |
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| 299 | #define CSCNTL0_0 ((TI_BASE+0x00)/4) |
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| 300 | #define CSCNTL0_1 ((TI_BASE+0x04)/4) |
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| 301 | #define CSCNTL0_2 ((TI_BASE+0x08)/4) |
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| 302 | #define CSCNTL0_3 ((TI_BASE+0x0C)/4) |
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| 303 | #define CSCNTL0_4 ((TI_BASE+0x10)/4) |
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| 304 | #define CSCNTL0_5 ((TI_BASE+0x14)/4) |
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| 305 | #define CSCNTL0_6 ((TI_BASE+0x18)/4) |
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| 306 | #define CSCNTL1_0 ((TI_BASE+0x20)/4) |
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| 307 | #define CSCNTL1_1 ((TI_BASE+0x24)/4) |
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| 308 | #define CSCNTL1_2 ((TI_BASE+0x28)/4) |
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| 309 | #define CSCNTL1_3 ((TI_BASE+0x2C)/4) |
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| 310 | #define CSCNTL1_4 ((TI_BASE+0x30)/4) |
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| 311 | #define CSCNTL1_5 ((TI_BASE+0x34)/4) |
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| 312 | #define CSCNTL1_6 ((TI_BASE+0x38)/4) |
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| 313 | #define CSGCNTL ((TI_BASE+0x40)/4) |
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| 314 | #define MUXADCNTL ((TI_BASE+0x48)/4) |
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| 315 | #define PORTCNTL ((TI_BASE+0x60)/4) |
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| 316 | #define DCC ((TI_BASE+0x78)/4) |
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| 317 | #define BRK0 ((TI_BASE+0x100)/4) |
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| 318 | #define BRK1 ((TI_BASE+0x104)/4) |
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| 319 | #define BRK2 ((TI_BASE+0x108)/4) |
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| 320 | #define BRK3 ((TI_BASE+0x10C)/4) |
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| 321 | #define BRK4 ((TI_BASE+0x110)/4) |
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| 322 | #define BRK5 ((TI_BASE+0x114)/4) |
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| 323 | #define BRK6 ((TI_BASE+0x118)/4) |
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| 324 | #define BRK7 ((TI_BASE+0x11C)/4) |
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| 325 | #define BRKMSK ((TI_BASE+0x140)/4) |
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| 326 | #define BRKSTAT ((TI_BASE+0x144)/4) |
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| 327 | #define SLEEPTIMER ((TI_BASE+0x204)/4) |
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| 328 | #define SLEEPCNTL ((TI_BASE+0x208)/4) |
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| 329 | |
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| 330 | /****************************************************************************** |
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| 331 | * BIT MASKS for Chip registers |
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| 332 | ****************************************************************************** |
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| 333 | */ |
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| 334 | |
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| 335 | /** TELEPHONE ANSWERING DEVICE BLOCK (TAD) */ |
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| 336 | |
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| 337 | /* TADCNTL register */ |
|---|
| 338 | #define IRQCNTL 0x01 |
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| 339 | #define CE_CNTL 0x02 |
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| 340 | #define MSKTAD 0x04 |
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| 341 | #define TAD_PAD_ENB 0x40 |
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| 342 | #define TADENB 0x80 |
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| 343 | |
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| 344 | /* TADSTAT register */ |
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| 345 | #define RBN 0x01 |
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| 346 | #define TRANSFER 0x02 |
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| 347 | #define ACTIVE 0x04 |
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| 348 | |
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| 349 | /* TADCMD register */ |
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| 350 | #define MSK_TADCMD 0x0F /* Mask on TADCMD */ |
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| 351 | #define CONTINUE 0x10 |
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| 352 | |
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| 353 | /** RADIO CONTROLER BLOCK (RC3) */ |
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| 354 | |
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| 355 | /* SLICECNTL register */ |
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| 356 | #define MSK_SLICEDL 0x07 /* Mask on SLICEDL field */ |
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| 357 | #define MSK_SCNTL 0x18 /* Mask on SCNTL field */ |
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| 358 | #define SELOCK 0x20 |
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| 359 | #define MSK_MUXSLICE 0xC0 |
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| 360 | |
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| 361 | /* RCIOCNTL0 register */ |
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| 362 | #define D2SBYPASS 0x01 |
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| 363 | #define DRBYPASS 0x02 |
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| 364 | #define RXINV 0x04 |
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| 365 | #define SELANT 0x10 |
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| 366 | #define ANT 0x20 |
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| 367 | #define LDINV0 0x40 |
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| 368 | #define LDINV1 0x80 |
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| 369 | |
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| 370 | /* RCIOCNTL1 register */ |
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| 371 | #define MSK_GPO 0x0F /* Mask on GPO field */ |
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| 372 | #define P00ENB 0x10 |
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| 373 | #define ABORT 0x20 |
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| 374 | #define TXIO 0x40 |
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| 375 | #define TXINV 0x80 |
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| 376 | |
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| 377 | /* RCIOCNTL2 register */ |
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| 378 | #define SELRFCLK 0x01 |
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| 379 | #define SELRXPWR 0x02 |
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| 380 | #define TXPWRINV 0x04 |
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| 381 | #define RXPWRINV 0x08 |
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| 382 | #define SYNTHPWR0INV 0x10 |
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| 383 | #define SYNTHPWR1INV 0x20 |
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| 384 | #define TXDRONINV 0x40 |
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| 385 | #define SELTXDRON 0x80 |
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| 386 | |
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| 387 | /* RCIOCNTL3 register */ |
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| 388 | #define D2SMODE 0x01 |
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| 389 | #define DRCNTL 0x02 |
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| 390 | #define MSK_SELGPO 0x0C /* Mask on SELGPO field */ |
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| 391 | #define MSK_SUSPANT 0x30 /* Mask on SUSO/ANT field */ |
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| 392 | |
|---|
| 393 | /* SHAPERCNTL register */ |
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| 394 | #define INV 0x01 |
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| 395 | #define MID 0x02 |
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| 396 | #define PWRDWN 0x04 |
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| 397 | #define DACENB 0x80 |
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| 398 | |
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| 399 | /* SYNTFCNTL register */ |
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| 400 | #define SYNT_FREQ 0x80 |
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| 401 | |
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| 402 | /* SYNTCNTL0 register */ |
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| 403 | #define PWRFREQ 0x01 |
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| 404 | #define CLKPHASE 0x08 |
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| 405 | #define LETYPE 0x10 |
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| 406 | #define RPIPEON 0x20 |
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| 407 | #define PWRSGN 0x40 |
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| 408 | #define OUTLOCK 0x80 |
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| 409 | |
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| 410 | /* SYNTCNTL1 register */ |
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| 411 | #define SLE0 0x01 |
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| 412 | #define SLE1 0x02 |
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| 413 | #define SLE2 0x04 |
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| 414 | #define LEMODE 0x08 |
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| 415 | #define LESEL 0x10 |
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| 416 | #define SCLK 0x20 |
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| 417 | #define SDATA 0x40 |
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| 418 | #define HPMODE_SYNT 0x80 |
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| 419 | |
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| 420 | /* SYNTCNTL2 register */ |
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| 421 | #define START_DONE 0x80 |
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| 422 | #define MSK_N 0x03 /* Mask on N field */ |
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| 423 | |
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| 424 | /* SYNTCNTL3 register */ |
|---|
| 425 | #define RXPWRDNSEN 0x01 |
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| 426 | #define RXPWRUNSEN 0x02 |
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| 427 | #define TXPWRDNSEN 0x04 |
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| 428 | #define TXPWRUNSEN 0x08 |
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| 429 | #define SEQCNTL 0x10 |
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| 430 | #define ALIGN 0x20 |
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| 431 | #define PLLWORD 0x40 |
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| 432 | #define PRESEQ 0x80 |
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| 433 | |
|---|
| 434 | /* RFSCAN register */ |
|---|
| 435 | #define MSK_RF 0x0F /* Mask on RF field */ |
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| 436 | #define RFMAX 0x80 |
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| 437 | |
|---|
| 438 | /* RSSIRANGE register */ |
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| 439 | #define MSK_VREFP 0x03 /* Mask on VREFP field */ |
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| 440 | #define MSK_VREFN 0x0C /* Mask on VREFN field */ |
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| 441 | |
|---|
| 442 | /* RSSICNTL register */ |
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| 443 | #define MSK_MODE_RSSI 0x03 /* Mask on MODE field */ |
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| 444 | #define MARKFF 0x04 |
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| 445 | #define TXMARK 0x08 |
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| 446 | #define ALL_RSSI 0x10 |
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| 447 | #define RSSIACT 0x20 |
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| 448 | #define RSSIDIS 0x40 |
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| 449 | #define RSSIENB 0x80 |
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| 450 | |
|---|
| 451 | /* RCCNTL register */ |
|---|
| 452 | #define RCCNTL_ENABLE 0x80 |
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| 453 | |
|---|
| 454 | /* ADCCNTL1 register */ |
|---|
| 455 | #define ADCSTART 0x80 |
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| 456 | #define SCAN 0x40 |
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| 457 | #define ADCENB 0x80 |
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| 458 | #define MSK_ADCSEL 0x07 |
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| 459 | |
|---|
| 460 | /* ADCCNTL2 register */ |
|---|
| 461 | #define ADCOVER1 0x01 |
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| 462 | #define ADCOVER2 0x02 |
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| 463 | #define ADCDWN1 0x04 |
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| 464 | #define ADCDWN2 0x08 |
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| 465 | |
|---|
| 466 | /** PLP BLOCK */ |
|---|
| 467 | |
|---|
| 468 | /* DCNTL0 register */ |
|---|
| 469 | #define TMUXINT 0x01 |
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| 470 | #define MUTEIP 0x02 |
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| 471 | #define Q1Q2_PLP 0x04 |
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| 472 | #define TRANSP 0x08 |
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| 473 | #define CRYPTALL 0x10 |
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| 474 | #define TXSENSE 0x20 |
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| 475 | #define ZACT 0x40 |
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| 476 | #define PLPENB 0x80 |
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| 477 | |
|---|
| 478 | /* DCNTL1 register */ |
|---|
| 479 | #define ONECT 0x10 |
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| 480 | #define WOMODE 0x40 |
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| 481 | #define WOENB 0x80 |
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| 482 | #define MSK_RPIPE 0x07 /* mask on RPIPE field */ |
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| 483 | |
|---|
| 484 | /* RXSYNCT register */ |
|---|
| 485 | #define PRSIZE 0x04 |
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| 486 | #define PREEN 0x08 |
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| 487 | #define PRETYPE 0x40 |
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| 488 | #define PROLONG 0x80 |
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| 489 | |
|---|
| 490 | #define MSK_SYCNT 0x30 /* mask on SYCNT field */ |
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| 491 | #define MSK_PTHR 0x03 /* mask on PTHR field */ |
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| 492 | |
|---|
| 493 | /* CLOCK_CORR register */ |
|---|
| 494 | #define SIGN 0x80 |
|---|
| 495 | |
|---|
| 496 | /* PRESYNC register */ |
|---|
| 497 | #define PRESENB 0x80 |
|---|
| 498 | |
|---|
| 499 | #define MSK_PRES 0x0F /* mask on PRES field */ |
|---|
| 500 | |
|---|
| 501 | /* PLPALIN register */ |
|---|
| 502 | #define SYNM 0x08 |
|---|
| 503 | #define BITSLIP 0x10 |
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| 504 | #define SLOTFAIL 0x20 |
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| 505 | #define DFFAIL 0x40 |
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| 506 | #define LONGDF 0x80 |
|---|
| 507 | #define MODE_PLPALIN 0x03 /* mask on PLP alignment mode */ |
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| 508 | |
|---|
| 509 | /* SUSPCNTL register */ |
|---|
| 510 | #define SUSPENB 0x01 |
|---|
| 511 | |
|---|
| 512 | /* TSTCNTL register */ |
|---|
| 513 | #define DISBSCR 0x01 |
|---|
| 514 | #define TX_TST 0x02 |
|---|
| 515 | #define DATADIR 0x04 |
|---|
| 516 | |
|---|
| 517 | /* TSTDST register */ |
|---|
| 518 | #define RDY 0x80 |
|---|
| 519 | |
|---|
| 520 | /** ENCRYPTION ENGINE */ |
|---|
| 521 | |
|---|
| 522 | /* EECNTL register */ |
|---|
| 523 | /* Bit ENABLE already defined */ |
|---|
| 524 | #define EECNTL_ENABLE 0x80 |
|---|
| 525 | |
|---|
| 526 | /** PAINT+ BLOCK */ |
|---|
| 527 | |
|---|
| 528 | /* PAINTCNTL register */ |
|---|
| 529 | #define MUTEDIS0 0x0001 |
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| 530 | #define MUTEDIS1 0x0002 |
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| 531 | #define MEMLOOP0 0x0004 |
|---|
| 532 | #define MEMLOOP1 0x0008 |
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| 533 | #define RATE0 0x0010 |
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| 534 | #define RATE1 0x0020 |
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| 535 | #define CHAN0ENB 0x0040 |
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| 536 | #define CHAN1ENB 0x0080 |
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| 537 | #define BG0ENABLE 0x0100 |
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| 538 | #define BG1ENABLE 0x0200 |
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| 539 | #define PADENABLE 0x2000 |
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| 540 | #define FORCE13 0x4000 |
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| 541 | #define PAINTENB 0x8000 |
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| 542 | |
|---|
| 543 | /* PAINTPLLCNTL register */ |
|---|
| 544 | #define MSK_MC 0x001F /* Mask on MC field */ |
|---|
| 545 | #define MCSIGN 0x0020 |
|---|
| 546 | #define MANUAL 0x0080 |
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| 547 | #define RANG0 0x0100 |
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| 548 | #define RANG1 0x0200 |
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| 549 | #define RANG2 0x0400 |
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| 550 | #define MSK_RANG 0x0700 /* Mask on RANG field */ |
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| 551 | #define FREEZD 0x1000 |
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| 552 | #define FREEZP 0x2000 |
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| 553 | #define PPFP 0x8000 |
|---|
| 554 | |
|---|
| 555 | /* PAINTPLLSTAT register */ |
|---|
| 556 | #define MSK_DPHI 0x01FF /* Mask on DPHI field */ |
|---|
| 557 | #define LOCKD 0x1000 |
|---|
| 558 | #define LOCKP 0x2000 |
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| 559 | #define NOSIG 0x8000 |
|---|
| 560 | |
|---|
| 561 | /* HPPCMCNTL register */ |
|---|
| 562 | #define LEN0 0x0001 |
|---|
| 563 | #define LEN1 0x0002 |
|---|
| 564 | #define LEN2 0x0004 |
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| 565 | #define MSK_LEN 0x0007 /* Mask on LEN field */ |
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| 566 | #define FREQ0 0x0010 |
|---|
| 567 | #define FREQ1 0x0020 |
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| 568 | #define MSK_PCMFREQ 0x0030 /* Mask on FREQ field */ |
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| 569 | #define FSTYP0 0x0100 |
|---|
| 570 | #define FSTYP1 0x0200 |
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| 571 | #define MSK_FSTYP 0x0300 /* Mask on FSTYP field */ |
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| 572 | #define IOD0 0x0400 |
|---|
| 573 | #define IOD1 0x0800 |
|---|
| 574 | #define MSK_IOD 0x0C00 /* Mask on FSTYP field */ |
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| 575 | #define IOCK 0x1000 |
|---|
| 576 | #define MASTER 0x4000 |
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| 577 | #define PCMENB 0x8000 |
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| 578 | |
|---|
| 579 | /* VBAFECNTL register */ |
|---|
| 580 | #define MSK_VOLMIC 0x0007 /* Mask on VOLMIV field */ |
|---|
| 581 | #define MICDIF 0x0010 |
|---|
| 582 | #define ENBMICREF 0x0080 |
|---|
| 583 | #define MODE0 0x0100 |
|---|
| 584 | #define MODE1 0x0200 |
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| 585 | #define MODE2 0x0400 |
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| 586 | #define LOOP0 0x1000 |
|---|
| 587 | #define LOOP1 0x2000 |
|---|
| 588 | #define FLOAT 0x4000 |
|---|
| 589 | #define VBAFENB 0x8000 |
|---|
| 590 | |
|---|
| 591 | /* VBAFEAMP register */ |
|---|
| 592 | #define MSK_VOL1OUT 0x000F /* Mask on VOL1OUT field */ |
|---|
| 593 | #define ENBCH1 0x0010 |
|---|
| 594 | #define MSK_VOL2OUT 0x0F00 /* Mask on VOL2OUT field */ |
|---|
| 595 | #define ENBCH2 0x1000 |
|---|
| 596 | |
|---|
| 597 | /* VBAFEPREAMP register */ |
|---|
| 598 | #define MSK_VOLIN 0x000F /* Mask on VOLIN field */ |
|---|
| 599 | #define MSK_ATT 0x0070 /* Mask on ATT field */ |
|---|
| 600 | #define PRCNF0 0x0100 |
|---|
| 601 | #define PRCNF1 0x0200 |
|---|
| 602 | #define PRCNF2 0x0400 |
|---|
| 603 | |
|---|
| 604 | /* MPDCNTL register */ |
|---|
| 605 | #define MPD_FREQ 0x0001 |
|---|
| 606 | #define MPD_ENB 0x0080 |
|---|
| 607 | |
|---|
| 608 | /* MPDREADY register */ |
|---|
| 609 | #define MPD_RDY 0x0001 |
|---|
| 610 | |
|---|
| 611 | /* G726CNTL0 register */ |
|---|
| 612 | #define RXTONE0 0x0001 |
|---|
| 613 | #define RXTONE1 0x0002 |
|---|
| 614 | #define TXTONE0 0x0004 |
|---|
| 615 | #define TXTONE1 0x0008 |
|---|
| 616 | #define SCALE0 0x0010 |
|---|
| 617 | #define SCALE1 0x0020 |
|---|
| 618 | #define MSK_SCALE 0x0030 /* Mask on SCALE field */ |
|---|
| 619 | |
|---|
| 620 | /* G726CNTL1 register */ |
|---|
| 621 | #define LAW 0x0001 |
|---|
| 622 | #define UPCM 0x0002 |
|---|
| 623 | #define G726_TXMUTE 0x0004 |
|---|
| 624 | #define G726_RXMUTE 0x0008 |
|---|
| 625 | #define SIDETONE 0x0010 |
|---|
| 626 | #define SCA 0x0020 |
|---|
| 627 | #define G726ENB 0x0080 |
|---|
| 628 | |
|---|
| 629 | /* G726CHANNEL register */ |
|---|
| 630 | #define CHAN 0x0002 |
|---|
| 631 | |
|---|
| 632 | /* G726CHANENB register */ |
|---|
| 633 | #define G726ENB0 0x0001 |
|---|
| 634 | #define G726ENB1 0x0003 |
|---|
| 635 | |
|---|
| 636 | /** GENERAL REGISTERS BLOCK */ |
|---|
| 637 | |
|---|
| 638 | /* RINGCNTL register */ |
|---|
| 639 | /* Bit ENABLE already defined */ |
|---|
| 640 | #define RINGCNTL_ENABLE 0x80 |
|---|
| 641 | #define FULL_BRIDGE 0x40 |
|---|
| 642 | #define MSK_DELAY 0x30 |
|---|
| 643 | #define RING_PADENB 0x08 |
|---|
| 644 | #define MSK_LEVEL 0x07 /* mask on LEVEL field */ |
|---|
| 645 | |
|---|
| 646 | /* RSIER register (UART Interrupt enable register definition) */ |
|---|
| 647 | #define LINE_STATUS_ENABLE 0x04 |
|---|
| 648 | #define TX_INT_ENABLE 0x02 |
|---|
| 649 | #define RX_INT_ENABLE 0x01 |
|---|
| 650 | |
|---|
| 651 | /* RSIIR register (UART Interrupt identification register definition) */ |
|---|
| 652 | #define FIFO_ENABLE_MASK 0xC0 |
|---|
| 653 | #define INT_ID_MASK 0x0E |
|---|
| 654 | #define PENDING_INT_FLAG 0x01 |
|---|
| 655 | #define LINE_STATUS_INT 0x06 /* values for interrupt identification */ |
|---|
| 656 | #define RX_INT 0x04 |
|---|
| 657 | #define FIFO_TIMEOUT_INT 0x0C |
|---|
| 658 | #define TX_EMPTY_INT 0x02 |
|---|
| 659 | |
|---|
| 660 | /* RSFCR register (UART Tx/Rx FIFO control register definition) */ |
|---|
| 661 | #define RX_LEVEL_MASK 0xC0 |
|---|
| 662 | #define CLEAR_TX_FIFO 0x04 |
|---|
| 663 | #define CLEAR_RX_FIFO 0x02 |
|---|
| 664 | #define FIFO_ENABLE 0x01 |
|---|
| 665 | #define _1_BYTE_RECEIVED 0x00 /* RX level values (Interrupt trigger ) */ |
|---|
| 666 | #define _4_BYTE_RECEIVED 0x40 |
|---|
| 667 | #define _8_BYTE_RECEIVED 0x80 |
|---|
| 668 | #define _14_BYTE_RECEIVED 0xC0 |
|---|
| 669 | |
|---|
| 670 | /* RSLCR register (UART line control register definition) */ |
|---|
| 671 | #define DIV_ENABLE 0x80 |
|---|
| 672 | #define TX_BREAK_ENABLE 0x40 |
|---|
| 673 | #define PARITY_ENABLE 0x08 |
|---|
| 674 | #define PARITY_MASK 0x30 |
|---|
| 675 | #define _1_STOP_BIT 0x00 |
|---|
| 676 | #define _2_STOP_BIT 0x04 |
|---|
| 677 | #define WORD_LENGTH_MASK 0x03 |
|---|
| 678 | #define ODD_PARITY 0x00 /* possible value for the parity */ |
|---|
| 679 | #define EVEN_PARITY 0x10 |
|---|
| 680 | #define PARITY_EQUAL1 0x20 |
|---|
| 681 | #define PARITY_EQUAL0 0x30 |
|---|
| 682 | #define _5_BITS_CHAR 0x00 /* possible value for the word length */ |
|---|
| 683 | #define _6_BITS_CHAR 0x01 |
|---|
| 684 | #define _7_BITS_CHAR 0x02 |
|---|
| 685 | #define _8_BITS_CHAR 0x03 |
|---|
| 686 | |
|---|
| 687 | /* RSLSR Register (UART line status register definition) */ |
|---|
| 688 | #define RX_FIFO_ERROR 0x80 |
|---|
| 689 | #define TXEMPTY 0x40 |
|---|
| 690 | #define HOLD_EMPTY 0x20 |
|---|
| 691 | #define BREAK 0x10 |
|---|
| 692 | #define FRAME_ERROR 0x08 |
|---|
| 693 | #define PARITY_ERROR 0x04 |
|---|
| 694 | #define OVERRUN_ERROR 0x02 |
|---|
| 695 | #define RX_READY 0x01 |
|---|
| 696 | |
|---|
| 697 | /* RSDLL Register (UART clock divider low register definition) */ |
|---|
| 698 | /* note RSDLH is always 0x00 */ |
|---|
| 699 | #define RS_4800 0x18 |
|---|
| 700 | #define RS_9600 0x0C |
|---|
| 701 | #define RS_19200 0x06 |
|---|
| 702 | #define RS_38400 0x03 |
|---|
| 703 | #define RS_57600 0x02 |
|---|
| 704 | #define RS_115200 0x01 |
|---|
| 705 | |
|---|
| 706 | /* RSCNT Register (UART control register definition) */ |
|---|
| 707 | #define UART_PAD_ENABLE 0x02 |
|---|
| 708 | |
|---|
| 709 | /* PWMCNTL register */ |
|---|
| 710 | #define PWMENB 0x80 |
|---|
| 711 | #define MSK_PWMFREQ 0x03 /* mask on PWMFREQ field */ |
|---|
| 712 | #define PWM1_PADENB 0x40 |
|---|
| 713 | #define PWM0_PADENB 0x20 |
|---|
| 714 | #define MIRROR 0x10 |
|---|
| 715 | |
|---|
| 716 | /* LCDEECNTL1 register */ |
|---|
| 717 | /* Bit ENABLE already defined */ |
|---|
| 718 | #define LCDEE_ENABLE 0x80 |
|---|
| 719 | #define DA1_DA0 0x40 |
|---|
| 720 | #define MSK_LCDEEFREQ 0x03 /* mask on LCDEEFREQ field */ |
|---|
| 721 | #define LCDEE_PADENB 0x40 |
|---|
| 722 | |
|---|
| 723 | /* LCDEECNTL2 register */ |
|---|
| 724 | #define SENDACK 0x01 |
|---|
| 725 | #define RXACK 0x02 |
|---|
| 726 | #define STOP 0x08 |
|---|
| 727 | #define START 0x10 |
|---|
| 728 | #define RX_LCDEE 0x20 |
|---|
| 729 | #define TX_LCDEE 0x40 |
|---|
| 730 | |
|---|
| 731 | /* DIAGCNTL1 register */ |
|---|
| 732 | #define DIAGL_PADENB 0x01 |
|---|
| 733 | #define DIAGH_PADENB 0x02 |
|---|
| 734 | |
|---|
| 735 | /* DIAGCNTL2 register */ |
|---|
| 736 | #define DLSEL 0x0F /* mask on DLSEL field */ |
|---|
| 737 | #define DHSEL 0xF0 /* mask on DHSEL field */ |
|---|
| 738 | |
|---|
| 739 | /* KEYROW register */ |
|---|
| 740 | #define MSK_ROW 0x1F /* mask on ROW field */ |
|---|
| 741 | #define KEYRELEASE 0x80 |
|---|
| 742 | |
|---|
| 743 | /* CLKCNTL register */ |
|---|
| 744 | #define MOSCDISABLE 0x02 |
|---|
| 745 | #define OVERSAM 0x04 |
|---|
| 746 | #define SQUARER 0x08 |
|---|
| 747 | #define SWRESET 0x80 |
|---|
| 748 | #define SWFLAG 0x80 |
|---|
| 749 | #define TSTN_DISABLE 0x40 |
|---|
| 750 | #define MODE55 0x10 |
|---|
| 751 | |
|---|
| 752 | /** THUMB and INTERFACES BLOCK */ |
|---|
| 753 | |
|---|
| 754 | /* CSCNTL0[6:0] registers */ |
|---|
| 755 | #define MSK_SETUP 0x0007 |
|---|
| 756 | #define SETUP_RD 0x0040 |
|---|
| 757 | #define SETUP_HZ 0x0080 |
|---|
| 758 | #define MSK_WIDTH 0x1F00 |
|---|
| 759 | #define MSK_HZWS 0xE000 |
|---|
| 760 | |
|---|
| 761 | /* CSCNTL1[6:0] registers */ |
|---|
| 762 | #define MSK_CSMODE 0x0003 |
|---|
| 763 | #define MSK_HOLD 0x0070 |
|---|
| 764 | #define HOLD_RD 0x0080 |
|---|
| 765 | #define MSK_WIDTH_WR 0x0700 |
|---|
| 766 | #define USE_WIDTH_WR 0x4000 |
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| 767 | #define WR_SHIFED 0x8000 |
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| 768 | |
|---|
| 769 | #define CSMODE_8 0x0000 |
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| 770 | #define CSMODE_16_WHWL 0x0002 |
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| 771 | #define CSMODE_16_BHBL 0x0003 |
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| 772 | |
|---|
| 773 | /* MUXADCNTL register */ |
|---|
| 774 | #define MSK_AHOLD 0x0007 |
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| 775 | #define MSK_ALEWIDTH 0x0070 |
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| 776 | |
|---|
| 777 | /* PORTCNTL register */ |
|---|
| 778 | #define CS0_ 0x0001 |
|---|
| 779 | #define CS1_ 0x0002 |
|---|
| 780 | #define CS2_ 0x0004 |
|---|
| 781 | #define CS3_ 0x0008 |
|---|
| 782 | #define CS4_ 0x0010 |
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| 783 | #define CS5_ 0x0020 |
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| 784 | #define CS6_ 0x0040 |
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| 785 | #define DATA_H 0x0080 |
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| 786 | #define INT0 0x0100 |
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| 787 | #define INT1 0x0200 |
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| 788 | #define INT2 0x0400 |
|---|
| 789 | #define INT3 0x0800 |
|---|
| 790 | #define MSK_ADDRESS 0x7000 |
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| 791 | #define EXTMEM 0x8000 |
|---|
| 792 | |
|---|
| 793 | #define ADDRESS_128K 0x0000 |
|---|
| 794 | #define ADDRESS_256K 0x1000 |
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| 795 | #define ADDRESS_512K 0x2000 |
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| 796 | #define ADDRESS_1M 0x3000 |
|---|
| 797 | #define ADDRESS_2M 0x4000 |
|---|
| 798 | |
|---|
| 799 | /* CSGCNTL register */ |
|---|
| 800 | #define CSSWITCH 0x0040 |
|---|
| 801 | |
|---|
| 802 | /* SLEEPCNTL register */ |
|---|
| 803 | #define EXPIRED 0x01 |
|---|
| 804 | #define SLEEP_ENABLE 0x80 |
|---|
| 805 | |
|---|
| 806 | /* WDCNTL register */ |
|---|
| 807 | #define WDSTROKE 0x80 |
|---|
| 808 | #define WDFLAG 0x80 /* same bit */ |
|---|
| 809 | |
|---|
| 810 | /* DCC register */ |
|---|
| 811 | /* bit ENABLE=0x80 already defined */ |
|---|
| 812 | #define DCC_ENABLE 0x80 |
|---|
| 813 | |
|---|
| 814 | /* TIMERCNTL[0:1] register */ |
|---|
| 815 | /* bit ENABLE=0x80 already defined */ |
|---|
| 816 | #define TIMER_ENABLE 0x80 |
|---|
| 817 | #define RELOAD 0x0040 |
|---|
| 818 | #define MSK_FREQ 0x0003 /* mask on FREQ field */ |
|---|
| 819 | #define TIMER_13824kHz 0x0003 |
|---|
| 820 | #define TIMER_864kHz 0x0002 |
|---|
| 821 | #define TIMER_216kHz 0x0001 |
|---|
| 822 | #define TIMER_27kHz 0x0000 |
|---|
| 823 | |
|---|
| 824 | /* INTMASKALL register */ |
|---|
| 825 | #define MASKIRQ 0x80 |
|---|
| 826 | #define MASKFIQ 0x40 |
|---|
| 827 | |
|---|
| 828 | /* INTEOI register */ |
|---|
| 829 | #define EOI 0x80 |
|---|
| 830 | |
|---|
| 831 | /* INTMASK register */ |
|---|
| 832 | /* INTSTAT register */ |
|---|
| 833 | /* INTIS register */ |
|---|
| 834 | |
|---|
| 835 | #define PLP 0x0001 |
|---|
| 836 | #define PCM 0x0002 |
|---|
| 837 | #define SRX 0x0004 |
|---|
| 838 | #define STX 0x0008 |
|---|
| 839 | #define TMR0 0x0010 |
|---|
| 840 | #define TMR1 0x0020 |
|---|
| 841 | #define LCDEE 0x0100 |
|---|
| 842 | #define KPAD 0x0200 |
|---|
| 843 | #define TAD 0x0400 |
|---|
| 844 | #define ADC 0x0800 |
|---|
| 845 | #define EXT0 0x1000 |
|---|
| 846 | #define EXT1 0x2000 |
|---|
| 847 | #define EXT2 0x4000 |
|---|
| 848 | #define EXT3 0x8000 |
|---|
| 849 | |
|---|
| 850 | /* INTCNTL[0:15] register */ |
|---|
| 851 | #define MSK_PRIO 0x0007 |
|---|
| 852 | #define RE 0x0008 |
|---|
| 853 | #define RISING 0x0040 |
|---|
| 854 | #define EDGE 0x0080 |
|---|
| 855 | |
|---|
| 856 | /* INTHPAI register */ |
|---|
| 857 | #define AUTOACK 0x0080 |
|---|
| 858 | |
|---|
| 859 | /****************************************************************************** |
|---|
| 860 | * Memory Mapping definition |
|---|
| 861 | ****************************************************************************** |
|---|
| 862 | */ |
|---|
| 863 | |
|---|
| 864 | #define CSN0_BASE_ADR 0x00200000 /* Base Address of CSN0 */ |
|---|
| 865 | #define CSN1_BASE_ADR 0x00400000 /* Base Address of CSN1 */ |
|---|
| 866 | #define CSN2_BASE_ADR 0x00600000 /* Base Address of CSN2 */ |
|---|
| 867 | #define CSN3_BASE_ADR 0x00800000 /* Base Address of CSN3 */ |
|---|
| 868 | #define CSN4_BASE_ADR 0x00A00000 /* Base Address of CSN4 */ |
|---|
| 869 | #define CSN5_BASE_ADR 0x00C00000 /* Base Address of CSN5 */ |
|---|
| 870 | #define CSN6_BASE_ADR 0x00E00000 /* Base Address of CSN6 */ |
|---|
| 871 | |
|---|
| 872 | #define IRAM_BASE_ADR 0x00000000 /* Base Addr. of int. Data Memory */ |
|---|
| 873 | #define SHRAM_BASE_ADR 0x00080000 /* Base Address of Share Memory */ |
|---|
| 874 | #define REGS_BASE_ADR 0x000F0000 /* Base Address of registers */ |
|---|
| 875 | #define RADRAM_BASE_ADR 0x000F0000 /* Base Address of registers */ |
|---|
| 876 | |
|---|
| 877 | /****************************************************************************** |
|---|
| 878 | * Slot Control bloc |
|---|
| 879 | ****************************************************************************** |
|---|
| 880 | */ |
|---|
| 881 | |
|---|
| 882 | #ifndef __asm__ |
|---|
| 883 | /*** Slot Control Block structure ***/ |
|---|
| 884 | typedef volatile struct /* normal Slot Control Block */ |
|---|
| 885 | { |
|---|
| 886 | unsigned char RAD0; |
|---|
| 887 | unsigned char RAD1; |
|---|
| 888 | unsigned char MODE; |
|---|
| 889 | unsigned char CNTL0; |
|---|
| 890 | unsigned char CNTL1; |
|---|
| 891 | unsigned char CNTL2; |
|---|
| 892 | unsigned char STAT0; |
|---|
| 893 | unsigned char STAT1; |
|---|
| 894 | unsigned char STAT2; |
|---|
| 895 | unsigned char CRYPT; |
|---|
| 896 | unsigned char MUTE; |
|---|
| 897 | unsigned char INT_; |
|---|
| 898 | unsigned char AMSG; |
|---|
| 899 | unsigned char AHDR; |
|---|
| 900 | unsigned short APTR; |
|---|
| 901 | unsigned short IPTR; |
|---|
| 902 | unsigned short CfPTR; |
|---|
| 903 | unsigned short OtPTR; |
|---|
| 904 | unsigned char OFFCNTL; |
|---|
| 905 | unsigned char WINCNTL; |
|---|
| 906 | } LM_SCB; |
|---|
| 907 | |
|---|
| 908 | typedef LM_SCB *LM_SCB_P; /* pointer to Slot Control Block */ |
|---|
| 909 | #endif |
|---|
| 910 | |
|---|
| 911 | /*** BIT MASKS for Slot Control Block parameters ***/ |
|---|
| 912 | |
|---|
| 913 | /* RAD0 parameter */ |
|---|
| 914 | #define RC_RSSIENB 0x80 /* RSSI measurement control */ |
|---|
| 915 | #define RC_ANTENNA2 0x08 /* antenna[2] selection */ |
|---|
| 916 | #define RC_ANTENNA1 0x04 /* antenna[1] selection */ |
|---|
| 917 | #define RC_ANTENNA0 0x02 /* antenna[0] selection */ |
|---|
| 918 | #define RC_SYNOUT 0x01 /* synthesiser selection */ |
|---|
| 919 | |
|---|
| 920 | #define RC_ANTSEL 0x0E /* mask on RC antenna selection */ |
|---|
| 921 | |
|---|
| 922 | /* RAD1 parameter */ |
|---|
| 923 | #define RC_RFC 0xF0 /* mask on RC RF carrier number */ |
|---|
| 924 | #define RC_RFSCAN 0x08 /* RF carrier source selection */ |
|---|
| 925 | #define RC_SYNLATCH 0x04 /* synthesizer #n Latch Enabled */ |
|---|
| 926 | #define RC_SYN_TX 0x03 /* slot is TX (synthesizer data) */ |
|---|
| 927 | #define RC_SYN_RX 0x02 /* slot is RX (synthesizer data) */ |
|---|
| 928 | |
|---|
| 929 | #define RC_SYNSLOT 0x03 /* mask on Synthesizer slot type */ |
|---|
| 930 | |
|---|
| 931 | /* MODE parameter */ |
|---|
| 932 | #define AUTOB1 0x80 |
|---|
| 933 | #define AUTOB0 0x40 |
|---|
| 934 | #define P00 0x20 |
|---|
| 935 | |
|---|
| 936 | #define MSK_MODE 0x1F /* mask on SCB MODE field */ |
|---|
| 937 | |
|---|
| 938 | /* CNTL0 parameter */ |
|---|
| 939 | #define LU7CH 0x80 |
|---|
| 940 | |
|---|
| 941 | #define MSK_BOFF 0x7F /* mask on BOFF field */ |
|---|
| 942 | |
|---|
| 943 | /* CNTL1 parameter */ |
|---|
| 944 | #define TX 0x80 |
|---|
| 945 | #define RESYNC 0x40 |
|---|
| 946 | #define Q1 0x40 /* Q1/RESYNC mapped on same bit */ |
|---|
| 947 | #define INHBST 0x20 |
|---|
| 948 | #define Q2 0x20 /* Q2/INHBST mapped on same bit */ |
|---|
| 949 | #define CTPACK 0x10 |
|---|
| 950 | |
|---|
| 951 | #define MSK_CTFLEN 0x0F /* mask on CTFLEN field */ |
|---|
| 952 | |
|---|
| 953 | /* CNTL2 parameter */ |
|---|
| 954 | #define SLTEN 0x80 |
|---|
| 955 | #define SINV 0x40 |
|---|
| 956 | #define ALL 0x20 |
|---|
| 957 | #define CO_CL 0x20 /* CO_CL/ALL mapped on same bit */ |
|---|
| 958 | #define INTEN 0x10 |
|---|
| 959 | #define SCOR1 0x08 |
|---|
| 960 | #define SCOR0 0x04 |
|---|
| 961 | #define BINTE 0x02 |
|---|
| 962 | #define BINTU 0x01 |
|---|
| 963 | |
|---|
| 964 | #define MSK_SCOR 0x0C /* mask on SCOR field */ |
|---|
| 965 | |
|---|
| 966 | /* STAT0 parameter */ |
|---|
| 967 | #define ZFAIL0 0x80 |
|---|
| 968 | #define ZFAIL1 0x40 |
|---|
| 969 | #define ZFAIL2 0x20 |
|---|
| 970 | #define ZFAIL3 0x10 |
|---|
| 971 | #define SCRD1 0x08 |
|---|
| 972 | #define SCRD0 0x04 |
|---|
| 973 | #define PRED1 0x02 |
|---|
| 974 | #define PRED0 0x01 |
|---|
| 975 | |
|---|
| 976 | #define MSK_ZFAIL 0xF0 /* mask on ZFAIL field */ |
|---|
| 977 | #define MSK_SCRD 0x0C /* mask on SCRD field */ |
|---|
| 978 | #define MSK_PRED 0x03 /* mask on PRED field */ |
|---|
| 979 | |
|---|
| 980 | /* STAT1 parameter */ |
|---|
| 981 | #define BCRC7 0x80 |
|---|
| 982 | #define BCRC6 0x40 |
|---|
| 983 | #define BCRC5 0x20 |
|---|
| 984 | #define BCRC4 0x10 |
|---|
| 985 | #define BCRC3 0x08 |
|---|
| 986 | #define BCRC2 0x04 |
|---|
| 987 | #define BCRC1 0x02 |
|---|
| 988 | #define BCRC0 0x01 |
|---|
| 989 | |
|---|
| 990 | /* STAT2 parameter */ |
|---|
| 991 | #define TMUX 0x80 |
|---|
| 992 | #define RADIO 0x40 |
|---|
| 993 | #define RFPI 0x20 |
|---|
| 994 | #define XCRC 0x10 |
|---|
| 995 | #define ACRC 0x08 |
|---|
| 996 | #define SYNC 0x04 |
|---|
| 997 | #define BCRC 0x02 |
|---|
| 998 | #define BCRC8 0x01 |
|---|
| 999 | |
|---|
| 1000 | /* CRYPT parameter */ |
|---|
| 1001 | #define LONG 0x80 |
|---|
| 1002 | #define INIP 0x40 |
|---|
| 1003 | #define ACRYPT 0x20 |
|---|
| 1004 | #define BCRYPT 0x10 |
|---|
| 1005 | |
|---|
| 1006 | #define MSK_EETBL 0x0F /* mask on EETBL field */ |
|---|
| 1007 | |
|---|
| 1008 | /* MUTE parameter */ |
|---|
| 1009 | #define NOTI 0x80 |
|---|
| 1010 | #define XFAIL 0x40 |
|---|
| 1011 | #define AFAIL 0x20 |
|---|
| 1012 | #define NOSYNC 0x10 /*NOSYNC/TXMUTE mapped on same bit*/ |
|---|
| 1013 | #define TXMUTE 0x10 |
|---|
| 1014 | |
|---|
| 1015 | #define MSK_CHAN 0x0F /* mask on CHAN field */ |
|---|
| 1016 | |
|---|
| 1017 | /* INT parameter */ |
|---|
| 1018 | /* Bit RADIO is already defined */ |
|---|
| 1019 | #define Q1Q2 0x80 |
|---|
| 1020 | #define RFP_I 0x20 |
|---|
| 1021 | #define X_CRC 0x10 |
|---|
| 1022 | #define R_CRC 0x08 |
|---|
| 1023 | #define SYNCFAIL 0x04 |
|---|
| 1024 | #define ASYNCOK 0x02 |
|---|
| 1025 | #define ZFIELD 0x01 |
|---|
| 1026 | |
|---|
| 1027 | /* AMSG parameter */ |
|---|
| 1028 | #define PP_FP 0x80 |
|---|
| 1029 | #define CT 0x40 |
|---|
| 1030 | #define NT 0x20 /* NT/CTSEND mapped on same bit */ |
|---|
| 1031 | #define CTSEND 0x20 |
|---|
| 1032 | #define MTFIRST 0x10 /* MTFIRST/QT mapped on same bit */ |
|---|
| 1033 | #define QT 0x10 |
|---|
| 1034 | #define MT 0x08 |
|---|
| 1035 | #define MTWAIT 0x04 |
|---|
| 1036 | #define PT 0x02 |
|---|
| 1037 | #define ESCAPE 0x01 |
|---|
| 1038 | |
|---|
| 1039 | /* WINCNTL parameter */ |
|---|
| 1040 | #define LM_WIN_NONE 0x00 /* no sync window */ |
|---|
| 1041 | #define LM_WIN_OPEN 0x3F /* wide open window size */ |
|---|
| 1042 | #define MSK_WINSZ 0x3F |
|---|
| 1043 | |
|---|
| 1044 | /* |
|---|
| 1045 | * Some macros to mask the VEGA+ interrupt sources |
|---|
| 1046 | ****************************************************************************** |
|---|
| 1047 | */ |
|---|
| 1048 | |
|---|
| 1049 | #define LM_MaskPLP() (LM_Regs[INTMASK] |= PLP) |
|---|
| 1050 | #define LM_MaskPCM() (LM_Regs[INTMASK] |= PCM) |
|---|
| 1051 | |
|---|
| 1052 | /* Vega+ product version */ |
|---|
| 1053 | #define LM_MaskUART() (LM_Regs[INTMASK] |= SRX) |
|---|
| 1054 | #define LM_MaskSRX() (LM_Regs[RSIER] &= ~RX_INT_ENABLE) |
|---|
| 1055 | #define LM_MaskSTX() (LM_Regs[RSIER] &= ~TX_INT_ENABLE) |
|---|
| 1056 | #define LM_MaskUARTStatus() (LM_Regs[RSIER] &= ~LINE_STATUS_ENABLE) |
|---|
| 1057 | |
|---|
| 1058 | #define LM_MaskTMR0() (LM_Regs[INTMASK] |= TMR0) |
|---|
| 1059 | #define LM_MaskTMR1() (LM_Regs[INTMASK] |= TMR1) |
|---|
| 1060 | #define LM_MaskLCDEE() (LM_Regs[INTMASK] |= LCDEE) |
|---|
| 1061 | #define LM_MaskKPAD() (LM_Regs[INTMASK] |= KPAD) |
|---|
| 1062 | #define LM_MaskTAD() (LM_Regs[INTMASK] |= TAD) |
|---|
| 1063 | #define LM_MaskADC() (LM_Regs[INTMASK] |= ADC) |
|---|
| 1064 | #define LM_MaskEXT0() (LM_Regs[INTMASK] |= EXT0) |
|---|
| 1065 | #define LM_MaskEXT1() (LM_Regs[INTMASK] |= EXT1) |
|---|
| 1066 | #define LM_MaskEXT2() (LM_Regs[INTMASK] |= EXT2) |
|---|
| 1067 | #define LM_MaskEXT3() (LM_Regs[INTMASK] |= EXT3) |
|---|
| 1068 | |
|---|
| 1069 | /* Some macros to ummask the VEGA+ interrupt sources */ |
|---|
| 1070 | #define LM_UnMaskPLP() (LM_Regs[INTMASK] &= ~PLP) |
|---|
| 1071 | #define LM_UnMaskPCM() (LM_Regs[INTMASK] &= ~PCM) |
|---|
| 1072 | |
|---|
| 1073 | /* Vega+ product version */ |
|---|
| 1074 | #define LM_UnMaskUART() (LM_Regs[INTMASK] &= ~SRX) |
|---|
| 1075 | #define LM_UnMaskSRX() (LM_Regs[RSIER] |= RX_INT_ENABLE) |
|---|
| 1076 | #define LM_UnMaskSTX() (LM_Regs[RSIER] |= TX_INT_ENABLE) |
|---|
| 1077 | #define LM_UnMaskUARTStatus() (LM_Regs[RSIER] |= LINE_STATUS_ENABLE) |
|---|
| 1078 | |
|---|
| 1079 | #define LM_UnMaskTMR0() (LM_Regs[INTMASK] &= ~TMR0) |
|---|
| 1080 | #define LM_UnMaskTMR1() (LM_Regs[INTMASK] &= ~TMR1) |
|---|
| 1081 | #define LM_UnMaskLCDEE() (LM_Regs[INTMASK] &= ~LCDEE) |
|---|
| 1082 | #define LM_UnMaskKPAD() (LM_Regs[INTMASK] &= ~KPAD) |
|---|
| 1083 | #define LM_UnMaskTAD() (LM_Regs[INTMASK] &= ~TAD) |
|---|
| 1084 | #define LM_UnMaskADC() (LM_Regs[INTMASK] &= ~ADC) |
|---|
| 1085 | #define LM_UnMaskEXT0() (LM_Regs[INTMASK] &= ~EXT0) |
|---|
| 1086 | #define LM_UnMaskEXT1() (LM_Regs[INTMASK] &= ~EXT1) |
|---|
| 1087 | #define LM_UnMaskEXT2() (LM_Regs[INTMASK] &= ~EXT2) |
|---|
| 1088 | #define LM_UnMaskEXT3() (LM_Regs[INTMASK] &= ~EXT3) |
|---|
| 1089 | |
|---|
| 1090 | /* Some macros to Acknoledge the VEGA+ interrupt sources */ |
|---|
| 1091 | #define LM_AckPLP() (LM_Regs[INTACK] |= PLP) |
|---|
| 1092 | #define LM_AckPCM() (LM_Regs[INTACK] |= PCM) |
|---|
| 1093 | #define LM_AckTMR0() (LM_Regs[INTACK] |= TMR0) |
|---|
| 1094 | #define LM_AckTMR1() (LM_Regs[INTACK] |= TMR1) |
|---|
| 1095 | #define LM_AckEXT0() (LM_Regs[INTACK] |= EXT0) |
|---|
| 1096 | #define LM_AckEXT1() (LM_Regs[INTACK] |= EXT1) |
|---|
| 1097 | #define LM_AckEXT2() (LM_Regs[INTACK] |= EXT2) |
|---|
| 1098 | #define LM_AckEXT3() (LM_Regs[INTACK] |= EXT3) |
|---|
| 1099 | |
|---|
| 1100 | /*#define INIT_LMREGS_MAPPING() { LM_Regs = (unsigned long*)REGS_BASE_ADR; }*/ |
|---|
| 1101 | |
|---|
| 1102 | #endif /*__LMREGS_H__*/ |
|---|
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