source: rtems/c/src/lib/libbsp/arm/tms570/startup/bspstart.c @ 38404cb

5
Last change on this file since 38404cb was 870ff8e9, checked in by Pavel Pisa <pisa@…>, on 11/12/15 at 22:11:31

bsp/tms570: use POM only when application image does not start at address 0.

Parameters overlay module is initialized and cleared first.
It is used later to replace exception target vectors
only if that is required.

The application loader code with CPU and SDRAM setup
code has to provide well defined pattern of instructions
at addresses 0x00000000 and 0x0000001f, because only data
read accesses can be processed reliably by POM. The expected
instruction pattern can be seen in the next example

https://github.com/hornmich/tms570ls3137-hdk-sdram/blob/master/SDRAM_SCI_configuration/source/sys_intvecs.asm

Comments with detailed description of code, background
and reasons for selected approach have been included
in TMS570 bsp startup code.

Signed-off-by: Pavel Pisa <pisa@…>
Signed-off-by: Premysl Houdek <kom541000@…>

  • Property mode set to 100644
File size: 2.0 KB
Line 
1/**
2 * @file bspstart.c
3 *
4 * @ingroup tms570
5 *
6 * @brief Startup code.
7 */
8
9/*
10 * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com>
11 *
12 * Google Summer of Code 2014 at
13 * Czech Technical University in Prague
14 * Zikova 1903/4
15 * 166 36 Praha 6
16 * Czech Republic
17 *
18 * Based on LPC24xx and LPC1768 BSP
19 *
20 * The license and distribution terms for this file may be
21 * found in the file LICENSE in this distribution or at
22 * http://www.rtems.org/license/LICENSE.
23 */
24
25#include <bsp.h>
26#include <bsp/tms570-pom.h>
27#include <bsp/irq-generic.h>
28#include <bsp/start.h>
29#include <bsp/bootcard.h>
30#include <bsp/linker-symbols.h>
31#include <rtems/endian.h>
32
33void bsp_start( void )
34{
35  #if BYTE_ORDER == BIG_ENDIAN
36    /*
37     * If CPU is big endian (TMS570 family variant)
38     * set the CPU mode to supervisor and big endian.
39     * Do not set mode if CPU is little endian
40     * (RM48 family variant) for which default mode 0x13
41     * defined in cpukit/score/cpu/arm/cpu.c
42     * is right.
43     */
44    arm_cpu_mode = 0x213;
45  #endif
46
47  tms570_initialize_and_clear();
48
49  /*
50   * If RTEMS image does not start at address 0x00000000
51   * then first level exception table at memory begin has
52   * to be replaced to point to RTEMS handlers addresses.
53   *
54   * There is no VBAR or other option because Cortex-R
55   * does provides only fixed address 0x00000000 for exceptions
56   * (0xFFFF0000-0xFFFF001C alternative SCTLR.V = 1 cannot
57   * be used because target area corersponds to PMM peripheral
58   * registers on TMS570).
59   *
60   * Alternative is to use jumps over SRAM based trampolines
61   * but that is not compatible with
62   *   Check TCRAM1 ECC error detection logic
63   * which intentionally introduces data abort during startup
64   * to check SRAM and if exception processing goes through
65   * SRAM then it leads to CPU error halt.
66   *
67   * So use of POM to replace jumps to vectors target
68   * addresses seems to be the best option.
69   */
70  if ( (uintptr_t)bsp_start_vector_table_begin != 0 ) {
71    tms570_pom_remap();
72  }
73
74  /* Interrupts */
75  bsp_interrupt_initialize();
76
77}
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