1 | /** |
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2 | * @file bspstart.c |
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3 | * |
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4 | * @ingroup tms570 |
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5 | * |
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6 | * @brief Startup code. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> |
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11 | * |
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12 | * Google Summer of Code 2014 at |
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13 | * Czech Technical University in Prague |
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14 | * Zikova 1903/4 |
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15 | * 166 36 Praha 6 |
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16 | * Czech Republic |
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17 | * |
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18 | * Based on LPC24xx and LPC1768 BSP |
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19 | * |
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20 | * The license and distribution terms for this file may be |
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21 | * found in the file LICENSE in this distribution or at |
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22 | * http://www.rtems.org/license/LICENSE. |
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23 | */ |
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24 | |
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25 | #include <bsp.h> |
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26 | #include <bsp/tms570-pom.h> |
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27 | #include <bsp/irq-generic.h> |
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28 | #include <bsp/start.h> |
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29 | #include <bsp/bootcard.h> |
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30 | #include <bsp/linker-symbols.h> |
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31 | #include <rtems/endian.h> |
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32 | |
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33 | void bsp_start( void ) |
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34 | { |
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35 | #if BYTE_ORDER == BIG_ENDIAN |
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36 | /* |
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37 | * If CPU is big endian (TMS570 family variant) |
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38 | * set the CPU mode to supervisor and big endian. |
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39 | * Do not set mode if CPU is little endian |
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40 | * (RM48 family variant) for which default mode 0x13 |
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41 | * defined in cpukit/score/cpu/arm/cpu.c |
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42 | * is right. |
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43 | */ |
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44 | arm_cpu_mode = 0x213; |
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45 | #endif |
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46 | |
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47 | tms570_initialize_and_clear(); |
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48 | |
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49 | /* |
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50 | * If RTEMS image does not start at address 0x00000000 |
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51 | * then first level exception table at memory begin has |
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52 | * to be replaced to point to RTEMS handlers addresses. |
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53 | * |
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54 | * There is no VBAR or other option because Cortex-R |
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55 | * does provides only fixed address 0x00000000 for exceptions |
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56 | * (0xFFFF0000-0xFFFF001C alternative SCTLR.V = 1 cannot |
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57 | * be used because target area corersponds to PMM peripheral |
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58 | * registers on TMS570). |
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59 | * |
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60 | * Alternative is to use jumps over SRAM based trampolines |
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61 | * but that is not compatible with |
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62 | * Check TCRAM1 ECC error detection logic |
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63 | * which intentionally introduces data abort during startup |
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64 | * to check SRAM and if exception processing goes through |
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65 | * SRAM then it leads to CPU error halt. |
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66 | * |
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67 | * So use of POM to replace jumps to vectors target |
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68 | * addresses seems to be the best option. |
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69 | */ |
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70 | if ( (uintptr_t)bsp_start_vector_table_begin != 0 ) { |
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71 | tms570_pom_remap(); |
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72 | } |
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73 | |
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74 | /* Interrupts */ |
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75 | bsp_interrupt_initialize(); |
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76 | |
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77 | } |
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