1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup tms570_clocks |
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5 | * |
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6 | * @brief Cortex-R performace counters |
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7 | * |
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8 | * The counters setup functions are these which has been suggested |
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9 | * on StackOverflow |
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10 | * |
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11 | * Code is probably for use on Cortex-A without modifications as well. |
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12 | * |
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13 | * http://stackoverflow.com/questions/3247373/how-to-measure-program-execution-time-in-arm-cortex-a8-processor |
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14 | */ |
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15 | |
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16 | /* |
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17 | * Copyright (c) 2014 Pavel Pisa <pisa@cmp.felk.cvut.cz> |
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18 | * |
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19 | * Czech Technical University in Prague |
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20 | * Zikova 1903/4 |
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21 | * 166 36 Praha 6 |
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22 | * Czech Republic |
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23 | * |
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24 | * The license and distribution terms for this file may be |
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25 | * found in the file LICENSE in this distribution or at |
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26 | * http://www.rtems.org/license/LICENSE. |
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27 | */ |
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28 | |
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29 | #include <rtems/counter.h> |
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30 | #include <rtems/sysinit.h> |
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31 | |
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32 | #include <bsp.h> |
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33 | |
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34 | /** |
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35 | * @brief set mode of Cortex-R performance counters |
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36 | * |
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37 | * Based on example found on http://stackoverflow.com |
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38 | * |
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39 | * @param[in] do_reset if set, values of the counters are reset |
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40 | * @param[in] enable_divider if set, CCNT counts clocks divided by 64 |
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41 | * @retval Void |
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42 | */ |
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43 | static inline void tms570_init_perfcounters( |
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44 | int32_t do_reset, |
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45 | int32_t enable_divider |
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46 | ) |
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47 | { |
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48 | /* in general enable all counters (including cycle counter) */ |
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49 | int32_t value = 1; |
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50 | |
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51 | /* peform reset */ |
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52 | if (do_reset) |
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53 | { |
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54 | value |= 2; /* reset all counters to zero */ |
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55 | value |= 4; /* reset cycle counter to zero */ |
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56 | } |
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57 | |
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58 | if (enable_divider) |
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59 | value |= 8; /* enable "by 64" divider for CCNT */ |
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60 | |
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61 | value |= 16; |
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62 | |
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63 | /* program the performance-counter control-register */ |
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64 | asm volatile ("mcr p15, 0, %0, c9, c12, 0\t\n" :: "r"(value)); |
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65 | |
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66 | /* enable all counters */ |
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67 | asm volatile ("mcr p15, 0, %0, c9, c12, 1\t\n" :: "r"(0x8000000f)); |
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68 | |
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69 | /* clear overflows */ |
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70 | asm volatile ("mcr p15, 0, %0, c9, c12, 3\t\n" :: "r"(0x8000000f)); |
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71 | } |
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72 | |
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73 | /** |
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74 | * @brief initialize Cortex-R performance counters subsystem |
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75 | * |
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76 | * Based on example found on http://stackoverflow.com |
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77 | * |
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78 | * @retval Void |
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79 | * |
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80 | */ |
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81 | static void tms570_cpu_counter_initialize(void) |
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82 | { |
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83 | /* enable user-mode access to the performance counter */ |
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84 | asm volatile ("mcr p15, 0, %0, c9, c14, 0\n\t" :: "r"(1)); |
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85 | |
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86 | /* disable counter overflow interrupts (just in case) */ |
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87 | asm volatile ("mcr p15, 0, %0, c9, c14, 2\n\t" :: "r"(0x8000000f)); |
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88 | |
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89 | tms570_init_perfcounters(false, false); |
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90 | rtems_counter_initialize_converter(2 * BSP_PLL_OUT_CLOCK); |
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91 | } |
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92 | |
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93 | /** |
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94 | * @brief returns the actual value of Cortex-R cycle counter register |
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95 | * |
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96 | * The register is incremented at each core clock period |
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97 | * |
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98 | * @retval x actual core clock counter value |
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99 | * |
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100 | */ |
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101 | CPU_Counter_ticks _CPU_Counter_read(void) |
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102 | { |
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103 | uint32_t ticks; |
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104 | asm volatile ("mrc p15, 0, %0, c9, c13, 0\n": "=r" (ticks)); |
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105 | return ticks; |
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106 | } |
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107 | |
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108 | RTEMS_SYSINIT_ITEM( |
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109 | tms570_cpu_counter_initialize, |
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110 | RTEMS_SYSINIT_BSP_START, |
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111 | RTEMS_SYSINIT_ORDER_FIRST |
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112 | ); |
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