4.115
Last change
on this file since 9588946 was
ec8f3cb,
checked in by Martin Galvan <martin.galvan@…>, on 03/26/15 at 20:16:38
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TMS570: Add board reset code to bsp_reset
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Property mode set to
100644
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File size:
973 bytes
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1 | /** |
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2 | * @file tms570.h |
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3 | * |
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4 | * @ingroup tms570 |
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5 | * |
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6 | * @brief Specific register definitions according to tms570 family boards. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2015 Taller Technologies. |
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11 | * |
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12 | * @author Martin Galvan <martin.galvan@tallertechnologies.com> |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | */ |
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18 | |
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19 | #ifndef LIBBSP_ARM_TMS570_H |
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20 | #define LIBBSP_ARM_TMS570_H |
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21 | |
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22 | #define SYSECR (*(uint32_t *)0xFFFFFFE0u) /* System Exception Control Register */ |
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23 | #define ESMIOFFHR (*(uint32_t *)0xFFFFF528) /* ESM Interrupt Offset High Register */ |
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24 | #define ESMSR1 (*(uint32_t *)0xFFFFF518u) /* ESM Status Register 1 */ |
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25 | #define ESMSR2 (*(uint32_t *)0xFFFFF51Cu) /* ESM Status Register 2 */ |
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26 | #define ESMSR3 (*(uint32_t *)0xFFFFF520u) /* ESM Status Register 3 */ |
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27 | #define ESMSR4 (*(uint32_t *)0xFFFFF558u) /* ESM Status Register 4 */ |
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28 | |
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29 | #define SYSECR_RESET 0x80000u |
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30 | |
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31 | #endif /* LIBBSP_ARM_TMS570_H */ |
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