source: rtems/c/src/lib/libbsp/arm/tms570/include/tms570-rti.h @ cf4dfc1

4.11
Last change on this file since cf4dfc1 was 4407ee6, checked in by Premysl Houdek <kom541000@…>, on Aug 20, 2014 at 3:24:23 PM

BSP for TMS570LS31x Hercules Development Kit from TI (TMS570LS3137)

Included variants:

tms570ls3137_hdk_intram - place code and data into internal SRAM
tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM
tms570ls3137_hdk - variant prepared for stand-alone RTEMS aplication

stored and running directly from flash. Not working yet.

Chip initialization code not included in BSP.
External startup generated by TI's HalCoGen? was used for
testing and debugging.

More information about TMS570 BSP can be found at

http://www.rtems.org/wiki/index.php/Tms570

Patch version 2

  • most of the formatting suggestion applied.
  • BSP converted to use clock shell
  • console driver "set attributes" tested. Baudrate change working

Patch version 3

  • more formatting changes.
  • removed leftover defines and test functions

Todo:

refactor header files (name register fields)

  • Property mode set to 100644
File size: 3.4 KB
Line 
1/**
2 * @file tms570-rti.h
3 *
4 * @ingroup tms570
5 *
6 * @brief Real Time Interrupt module (RTI) header file.
7 */
8
9/*
10 * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com>
11 *
12 * Google Summer of Code 2014 at
13 * Czech Technical University in Prague
14 * Zikova 1903/4
15 * 166 36 Praha 6
16 * Czech Republic
17 *
18 * Based on LPC24xx and LPC1768 BSP
19 * by embedded brains GmbH and others
20 *
21 * The license and distribution terms for this file may be
22 * found in the file LICENSE in this distribution or at
23 * http://www.rtems.org/license/LICENSE.
24 */
25
26#ifndef LIBBSP_ARM_TMS570_RTI_H
27#define LIBBSP_ARM_TMS570_RTI_H
28
29#ifndef ASM
30
31#include <stdint.h>
32
33#ifdef __cplusplus
34extern "C" {
35#endif /* __cplusplus */
36
37typedef struct {
38  uint32_t RTIGCTRL;       /* RTIGlobalControlRegister */
39  uint32_t RTITBCTRL;      /* RTITimebaseControlRegister */
40  uint32_t RTICAPCTRL;     /* RTICaptureControlRegister */
41  uint32_t RTICOMPCTRL;    /* RTICompareControlRegister */
42  uint32_t RTIFRC0;        /* RTIFreeRunningCounter0Register */
43  uint32_t RTIUC0;         /* RTIUpCounter0Register */
44  uint32_t RTICPUC0;       /* RTICompareUpCounter0Register */
45  uint32_t reserved1 [0x4/4];
46  uint32_t RTICAFRC0;      /* RTICaptureFreeRunningCounter0Register */
47  uint32_t RTICAUC0;       /* RTICaptureUpCounter0Register */
48  uint32_t reserved2 [0x8/4];
49  uint32_t RTIFRC1;        /* RTIFreeRunningCounter1Register */
50  uint32_t RTIUC1;         /* RTIUpCounter1Register */
51  uint32_t RTICPUC1;       /* RTICompareUpCounter1Register */
52  uint32_t reserved3 [0x4/4];
53  uint32_t RTICAFRC1;      /* RTICaptureFreeRunningCounter1Register */
54  uint32_t RTICAUC1;       /* RTICaptureUpCounter1Register */
55  uint32_t reserved4 [0x8/4];
56  uint32_t RTICOMP0;       /* RTICompare0Register */
57  uint32_t RTIUDCP0;       /* RTIUpdateCompare0Register */
58  uint32_t RTICOMP1;       /* RTICompare1Register */
59  uint32_t RTIUDCP1;       /* RTIUpdateCompare1Register */
60  uint32_t RTICOMP2;       /* RTICompare2Register */
61  uint32_t RTIUDCP2;       /* RTIUpdateCompare2Register */
62  uint32_t RTICOMP3;       /* RTICompare3Register */
63  uint32_t RTIUDCP3;       /* RTIUpdateCompare3Register */
64  uint32_t RTITBLCOMP;     /* RTITimebaseLowCompareRegister */
65  uint32_t RTITBHCOMP;     /* RTITimebaseHighCompareRegister */
66  uint32_t reserved5 [0x8/4];
67  uint32_t RTISETINTENA;   /* RTISetInterruptEnableRegister */
68  uint32_t RTICLEARINTENA; /* RTIClearInterruptEnableRegister */
69  uint32_t RTIINTFLAG;     /* RTIInterruptFlagRegister */
70  uint32_t reserved6 [0x4/4];
71  uint32_t RTIDWDCTRL;     /* DigitalWatchdogControlRegister */
72  uint32_t RTIDWDPRLD;     /* DigitalWatchdogPreloadRegister */
73  uint32_t RTIWDSTATUS;    /* WatchdogStatusRegister */
74  uint32_t RTIWDKEY;       /* RTIWatchdogKeyRegister */
75  uint32_t RTIDWDCNTR;     /* RTIDigitalWatchdogDownCounterRegister */
76  uint32_t RTIWWDRXNCTRL;  /* DigitalWindowedWatchdogReactionControlRegister */
77  uint32_t RTIWWDSIZECTRL; /* DigitalWindowedWatchdogWindowSizeControlRegister */
78  uint32_t RTIINTCLRENABLE;/* RTICompareInterruptClearEnableRegister */
79  uint32_t RTICOMP0CLR;    /* RTICompare0ClearRegister */
80  uint32_t RTICOMP1CLR;    /* RTICompare1ClearRegister */
81  uint32_t RTICOMP2CLR;    /* RTICompare2ClearRegister */
82  uint32_t RTICOMP3CLR;    /* RTICompare3ClearRegister */
83}tms570_rti_t;
84
85#define TMS570_RTI (*(volatile tms570_rti_t*)0xFFFFFC00)
86
87/** @} */
88
89#ifdef __cplusplus
90}
91#endif /* __cplusplus */
92
93#endif /* ASM */
94
95#endif /* LIBBSP_ARM_TMS570_IRQ_H */
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