source: rtems/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_vim.h @ bea49c9

4.11
Last change on this file since bea49c9 was bea49c9, checked in by Premysl Houdek <kom541000@…>, on Jul 16, 2015 at 2:26:09 PM

bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.

The header files are generated by script make_header.py.
Current script's version can be found at:

https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python

Registers offsets and fields have been extracted from reference manual.

Signed-off-by: Premysl Houdek <kom541000@…>

  • Property mode set to 100644
File size: 10.6 KB
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1/* The header file is generated by make_header.py from VIM.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_tms570_VIM
40#define LIBBSP_ARM_tms570_VIM
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t PARFLG;            /*Interrupt Vector Table Parity Flag Register*/
46  uint32_t PARCTL;            /*Interrupt Vector Table Parity Control Register*/
47  uint32_t ADDERR;            /*Address Parity Error Register*/
48  uint32_t FBPARERR;          /*Fall-Back Address Parity Error Register*/
49  uint8_t reserved1 [4];
50  uint32_t IRQINDEX;          /*IRQ Index Offset Vector Register*/
51  uint32_t FIQINDEX;          /*FIQ Index Offset Vector Register*/
52  uint8_t reserved2 [8];
53  uint32_t FIRQPR[3];         /*FIQ/IRQ Program Control Register*/
54  uint8_t reserved3 [4];
55  uint32_t INTREQ[3];         /*Pending Interrupt Read Location Register*/
56  uint8_t reserved4 [4];
57  uint32_t REQENASET[3];      /*Interrupt Enable Set Register */
58  uint8_t reserved5 [4];
59  uint32_t REQENACLR[3];      /*Interrupt Enable Clear Register */
60  uint8_t reserved6 [4];
61  uint32_t WAKEENASET[3];     /*Wake-Up Enable Set Register*/
62  uint8_t reserved7 [4];
63  uint32_t WAKEENACLR[3];     /*Wake-Up Enable Clear Registers*/
64  uint8_t reserved8 [4];
65  uint32_t IRQVECREG;         /*IRQ Interrupt Vector Register*/
66  uint32_t FIQVECREG;         /*FIQ Interrupt Vector Register*/
67  uint32_t CAPEVT;            /*Capture Event Register*/
68  uint8_t reserved9 [4];
69  uint32_t CHANCTRL[24];      /*VIM Interrupt Control Register*/
70} tms570_vim_t;
71
72
73/*----------------------TMS570_VIMPARFLG----------------------*/
74/* field: PARFLG - The PARFLG indicates that a parity error has been found and that theInterrupt Vector Table is */
75#define TMS570_VIM_PARFLG_PARFLG BSP_FLD32(0)
76
77
78/*----------------------TMS570_VIMPARCTL----------------------*/
79/* field: TEST - This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by the */
80#define TMS570_VIM_PARCTL_TEST BSP_FLD32(8)
81
82/* field: PARENA - VIM parity enable. */
83#define TMS570_VIM_PARCTL_PARENA(val) BSP_FLD32(val,0, 3)
84#define TMS570_VIM_PARCTL_PARENA_GET(reg) BSP_FLD32GET(reg,0, 3)
85#define TMS570_VIM_PARCTL_PARENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
86
87
88/*----------------------TMS570_VIMADDERR----------------------*/
89/* field: Interrupt_Vector_Table - Interrupt Vector Table offset. */
90#define TMS570_VIM_ADDERR_Interrupt_Vector_Table(val) BSP_FLD32(val,9, 31)
91#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_GET(reg) BSP_FLD32GET(reg,9, 31)
92#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_SET(reg,val) BSP_FLD32SET(reg, val,9, 31)
93
94/* field: ADDERR - Address parity error register. */
95#define TMS570_VIM_ADDERR_ADDERR(val) BSP_FLD32(val,2, 8)
96#define TMS570_VIM_ADDERR_ADDERR_GET(reg) BSP_FLD32GET(reg,2, 8)
97#define TMS570_VIM_ADDERR_ADDERR_SET(reg,val) BSP_FLD32SET(reg, val,2, 8)
98
99/* field: Word_offset - Word offset. Reads are always 0; writes have no effect. */
100#define TMS570_VIM_ADDERR_Word_offset(val) BSP_FLD32(val,0, 1)
101#define TMS570_VIM_ADDERR_Word_offset_GET(reg) BSP_FLD32GET(reg,0, 1)
102#define TMS570_VIM_ADDERR_Word_offset_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
103
104
105/*---------------------TMS570_VIMFBPARERR---------------------*/
106/* field: FBPARERR - Fall back address parity error. */
107#define TMS570_VIM_FBPARERR_FBPARERR(val) BSP_FLD32(val,0, 31)
108#define TMS570_VIM_FBPARERR_FBPARERR_GET(reg) BSP_FLD32GET(reg,0, 31)
109#define TMS570_VIM_FBPARERR_FBPARERR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
110
111
112/*---------------------TMS570_VIMIRQINDEX---------------------*/
113/* field: IRQINDEX - IRQ index vector. */
114#define TMS570_VIM_IRQINDEX_IRQINDEX(val) BSP_FLD32(val,0, 7)
115#define TMS570_VIM_IRQINDEX_IRQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
116#define TMS570_VIM_IRQINDEX_IRQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
117
118
119/*---------------------TMS570_VIMFIQINDEX---------------------*/
120/* field: FIQINDEX - FIQ index offset vector. */
121#define TMS570_VIM_FIQINDEX_FIQINDEX(val) BSP_FLD32(val,0, 7)
122#define TMS570_VIM_FIQINDEX_FIQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
123#define TMS570_VIM_FIQINDEX_FIQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
124
125
126/*----------------------TMS570_VIMFIRQPR----------------------*/
127/* field: FIRQPRx - FIQ/IRQ program control bits. 96 bit register. 0-1 bits reserved. */
128#define TMS570_VIM_FIRQPR_FIRQPRx(val) BSP_FLD32(val,0, 31)
129#define TMS570_VIM_FIRQPR_FIRQPRx_GET(reg) BSP_FLD32GET(reg,0, 31)
130#define TMS570_VIM_FIRQPR_FIRQPRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
131
132
133/*----------------------TMS570_VIMINTREQ----------------------*/
134/* field: INTREQx - Pending interrupt bits. 96 bit register. */
135#define TMS570_VIM_INTREQ_INTREQx(val) BSP_FLD32(val,0, 31)
136#define TMS570_VIM_INTREQ_INTREQx_GET(reg) BSP_FLD32GET(reg,0, 31)
137#define TMS570_VIM_INTREQ_INTREQx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
138
139
140/*--------------------TMS570_VIMREQENASET--------------------*/
141/* field: REQENASETx - Request enable set bits. 96 bit register. 0-1 bits reserved. */
142#define TMS570_VIM_REQENASET_REQENASETx(val) BSP_FLD32(val,0, 31)
143#define TMS570_VIM_REQENASET_REQENASETx_GET(reg) BSP_FLD32GET(reg,0, 31)
144#define TMS570_VIM_REQENASET_REQENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
145
146
147/*--------------------TMS570_VIMREQENACLR--------------------*/
148/* field: REQENACLRx - Request enable clear bits. 96 bit register. 0-1 bits reserved. */
149#define TMS570_VIM_REQENACLR_REQENACLRx(val) BSP_FLD32(val,0, 31)
150#define TMS570_VIM_REQENACLR_REQENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31)
151#define TMS570_VIM_REQENACLR_REQENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
152
153
154/*--------------------TMS570_VIMWAKEENASET--------------------*/
155/* field: WAKEENASETx - Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled. */
156#define TMS570_VIM_WAKEENASET_WAKEENASETx(val) BSP_FLD32(val,0, 31)
157#define TMS570_VIM_WAKEENASET_WAKEENASETx_GET(reg) BSP_FLD32GET(reg,0, 31)
158#define TMS570_VIM_WAKEENASET_WAKEENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
159
160
161/*--------------------TMS570_VIMWAKEENACLR--------------------*/
162/* field: WAKEENACLRx - Wake-up enable clear bits. This vector determines whether the wake-up interrupt line is enabled. */
163#define TMS570_VIM_WAKEENACLR_WAKEENACLRx(val) BSP_FLD32(val,0, 31)
164#define TMS570_VIM_WAKEENACLR_WAKEENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31)
165#define TMS570_VIM_WAKEENACLR_WAKEENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
166
167
168/*--------------------TMS570_VIMIRQVECREG--------------------*/
169/* field: IRQVECREG - IRQ interrupt vector register. */
170#define TMS570_VIM_IRQVECREG_IRQVECREG(val) BSP_FLD32(val,0, 31)
171#define TMS570_VIM_IRQVECREG_IRQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31)
172#define TMS570_VIM_IRQVECREG_IRQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
173
174
175/*--------------------TMS570_VIMFIQVECREG--------------------*/
176/* field: FIQVECREG - FIQ interrupt vector register. */
177#define TMS570_VIM_FIQVECREG_FIQVECREG(val) BSP_FLD32(val,0, 31)
178#define TMS570_VIM_FIQVECREG_FIQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31)
179#define TMS570_VIM_FIQVECREG_FIQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
180
181
182/*----------------------TMS570_VIMCAPEVT----------------------*/
183/* field: CAPEVTSRC1 - Capture event source 1 mapping control. */
184#define TMS570_VIM_CAPEVT_CAPEVTSRC1(val) BSP_FLD32(val,16, 22)
185#define TMS570_VIM_CAPEVT_CAPEVTSRC1_GET(reg) BSP_FLD32GET(reg,16, 22)
186#define TMS570_VIM_CAPEVT_CAPEVTSRC1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22)
187
188/* field: CAPEVTSRC0 - the capture event source 0 of the RTI: */
189#define TMS570_VIM_CAPEVT_CAPEVTSRC0(val) BSP_FLD32(val,0, 6)
190#define TMS570_VIM_CAPEVT_CAPEVTSRC0_GET(reg) BSP_FLD32GET(reg,0, 6)
191#define TMS570_VIM_CAPEVT_CAPEVTSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
192
193
194/*---------------------TMS570_VIMCHANCTRL---------------------*/
195/* field: CHANMAPx0 - CHANMAPx 0(6-0). Interrupt CHANx 0 mapping control. */
196#define TMS570_VIM_CHANCTRL_CHANMAPx0(val) BSP_FLD32(val,24, 30)
197#define TMS570_VIM_CHANCTRL_CHANMAPx0_GET(reg) BSP_FLD32GET(reg,24, 30)
198#define TMS570_VIM_CHANCTRL_CHANMAPx0_SET(reg,val) BSP_FLD32SET(reg, val,24, 30)
199
200/* field: CHANMAPx1 - CHANMAPx 1(6-0). Interrupt CHANx 1 mapping control. */
201#define TMS570_VIM_CHANCTRL_CHANMAPx1(val) BSP_FLD32(val,16, 22)
202#define TMS570_VIM_CHANCTRL_CHANMAPx1_GET(reg) BSP_FLD32GET(reg,16, 22)
203#define TMS570_VIM_CHANCTRL_CHANMAPx1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22)
204
205/* field: CHANMAPx2 - CHANMAPx 2(6-0). Interrupt CHANx 2 mapping control. */
206#define TMS570_VIM_CHANCTRL_CHANMAPx2(val) BSP_FLD32(val,8, 14)
207#define TMS570_VIM_CHANCTRL_CHANMAPx2_GET(reg) BSP_FLD32GET(reg,8, 14)
208#define TMS570_VIM_CHANCTRL_CHANMAPx2_SET(reg,val) BSP_FLD32SET(reg, val,8, 14)
209
210/* field: CHANMAPx3 - CHANMAPx 3(6-0). Interrupt CHANx 3 mapping control. */
211#define TMS570_VIM_CHANCTRL_CHANMAPx3(val) BSP_FLD32(val,0, 6)
212#define TMS570_VIM_CHANCTRL_CHANMAPx3_GET(reg) BSP_FLD32GET(reg,0, 6)
213#define TMS570_VIM_CHANCTRL_CHANMAPx3_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
214
215
216
217#endif /* LIBBSP_ARM_tms570_VIM */
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