[bea49c9] | 1 | /* The header file is generated by make_header.py from VIM.json */ |
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| 2 | /* Current script's version can be found at: */ |
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| 3 | /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ |
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| 4 | |
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| 5 | /* |
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| 6 | * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> |
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| 7 | * |
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| 8 | * Czech Technical University in Prague |
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| 9 | * Zikova 1903/4 |
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| 10 | * 166 36 Praha 6 |
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| 11 | * Czech Republic |
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| 12 | * |
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| 13 | * All rights reserved. |
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| 14 | * |
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| 15 | * Redistribution and use in source and binary forms, with or without |
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| 16 | * modification, are permitted provided that the following conditions are met: |
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| 17 | * |
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| 18 | * 1. Redistributions of source code must retain the above copyright notice, this |
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| 19 | * list of conditions and the following disclaimer. |
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| 20 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 21 | * this list of conditions and the following disclaimer in the documentation |
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| 22 | * and/or other materials provided with the distribution. |
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| 23 | * |
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
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| 25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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| 26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR |
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| 28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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| 29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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| 31 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 34 | * |
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| 35 | * The views and conclusions contained in the software and documentation are those |
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| 36 | * of the authors and should not be interpreted as representing official policies, |
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| 37 | * either expressed or implied, of the FreeBSD Project. |
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| 38 | */ |
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| 39 | #ifndef LIBBSP_ARM_tms570_VIM |
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| 40 | #define LIBBSP_ARM_tms570_VIM |
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| 41 | |
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| 42 | #include <bsp/utility.h> |
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| 43 | |
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| 44 | typedef struct{ |
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| 45 | uint32_t PARFLG; /*Interrupt Vector Table Parity Flag Register*/ |
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| 46 | uint32_t PARCTL; /*Interrupt Vector Table Parity Control Register*/ |
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| 47 | uint32_t ADDERR; /*Address Parity Error Register*/ |
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| 48 | uint32_t FBPARERR; /*Fall-Back Address Parity Error Register*/ |
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| 49 | uint8_t reserved1 [4]; |
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| 50 | uint32_t IRQINDEX; /*IRQ Index Offset Vector Register*/ |
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| 51 | uint32_t FIQINDEX; /*FIQ Index Offset Vector Register*/ |
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| 52 | uint8_t reserved2 [8]; |
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| 53 | uint32_t FIRQPR[3]; /*FIQ/IRQ Program Control Register*/ |
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| 54 | uint8_t reserved3 [4]; |
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| 55 | uint32_t INTREQ[3]; /*Pending Interrupt Read Location Register*/ |
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| 56 | uint8_t reserved4 [4]; |
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| 57 | uint32_t REQENASET[3]; /*Interrupt Enable Set Register */ |
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| 58 | uint8_t reserved5 [4]; |
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| 59 | uint32_t REQENACLR[3]; /*Interrupt Enable Clear Register */ |
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| 60 | uint8_t reserved6 [4]; |
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| 61 | uint32_t WAKEENASET[3]; /*Wake-Up Enable Set Register*/ |
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| 62 | uint8_t reserved7 [4]; |
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| 63 | uint32_t WAKEENACLR[3]; /*Wake-Up Enable Clear Registers*/ |
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| 64 | uint8_t reserved8 [4]; |
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| 65 | uint32_t IRQVECREG; /*IRQ Interrupt Vector Register*/ |
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| 66 | uint32_t FIQVECREG; /*FIQ Interrupt Vector Register*/ |
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| 67 | uint32_t CAPEVT; /*Capture Event Register*/ |
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| 68 | uint8_t reserved9 [4]; |
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| 69 | uint32_t CHANCTRL[24]; /*VIM Interrupt Control Register*/ |
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| 70 | } tms570_vim_t; |
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| 71 | |
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| 72 | |
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| 73 | /*----------------------TMS570_VIMPARFLG----------------------*/ |
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| 74 | /* field: PARFLG - The PARFLG indicates that a parity error has been found and that theInterrupt Vector Table is */ |
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| 75 | #define TMS570_VIM_PARFLG_PARFLG BSP_FLD32(0) |
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| 76 | |
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| 77 | |
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| 78 | /*----------------------TMS570_VIMPARCTL----------------------*/ |
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| 79 | /* field: TEST - This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by the */ |
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| 80 | #define TMS570_VIM_PARCTL_TEST BSP_FLD32(8) |
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| 81 | |
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| 82 | /* field: PARENA - VIM parity enable. */ |
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| 83 | #define TMS570_VIM_PARCTL_PARENA(val) BSP_FLD32(val,0, 3) |
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| 84 | #define TMS570_VIM_PARCTL_PARENA_GET(reg) BSP_FLD32GET(reg,0, 3) |
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| 85 | #define TMS570_VIM_PARCTL_PARENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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| 86 | |
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| 87 | |
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| 88 | /*----------------------TMS570_VIMADDERR----------------------*/ |
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| 89 | /* field: Interrupt_Vector_Table - Interrupt Vector Table offset. */ |
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| 90 | #define TMS570_VIM_ADDERR_Interrupt_Vector_Table(val) BSP_FLD32(val,9, 31) |
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| 91 | #define TMS570_VIM_ADDERR_Interrupt_Vector_Table_GET(reg) BSP_FLD32GET(reg,9, 31) |
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| 92 | #define TMS570_VIM_ADDERR_Interrupt_Vector_Table_SET(reg,val) BSP_FLD32SET(reg, val,9, 31) |
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| 93 | |
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| 94 | /* field: ADDERR - Address parity error register. */ |
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| 95 | #define TMS570_VIM_ADDERR_ADDERR(val) BSP_FLD32(val,2, 8) |
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| 96 | #define TMS570_VIM_ADDERR_ADDERR_GET(reg) BSP_FLD32GET(reg,2, 8) |
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| 97 | #define TMS570_VIM_ADDERR_ADDERR_SET(reg,val) BSP_FLD32SET(reg, val,2, 8) |
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| 98 | |
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| 99 | /* field: Word_offset - Word offset. Reads are always 0; writes have no effect. */ |
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| 100 | #define TMS570_VIM_ADDERR_Word_offset(val) BSP_FLD32(val,0, 1) |
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| 101 | #define TMS570_VIM_ADDERR_Word_offset_GET(reg) BSP_FLD32GET(reg,0, 1) |
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| 102 | #define TMS570_VIM_ADDERR_Word_offset_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) |
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| 103 | |
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| 104 | |
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| 105 | /*---------------------TMS570_VIMFBPARERR---------------------*/ |
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| 106 | /* field: FBPARERR - Fall back address parity error. */ |
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| 107 | #define TMS570_VIM_FBPARERR_FBPARERR(val) BSP_FLD32(val,0, 31) |
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| 108 | #define TMS570_VIM_FBPARERR_FBPARERR_GET(reg) BSP_FLD32GET(reg,0, 31) |
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| 109 | #define TMS570_VIM_FBPARERR_FBPARERR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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| 110 | |
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| 111 | |
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| 112 | /*---------------------TMS570_VIMIRQINDEX---------------------*/ |
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| 113 | /* field: IRQINDEX - IRQ index vector. */ |
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| 114 | #define TMS570_VIM_IRQINDEX_IRQINDEX(val) BSP_FLD32(val,0, 7) |
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| 115 | #define TMS570_VIM_IRQINDEX_IRQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7) |
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| 116 | #define TMS570_VIM_IRQINDEX_IRQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) |
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| 117 | |
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| 118 | |
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| 119 | /*---------------------TMS570_VIMFIQINDEX---------------------*/ |
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| 120 | /* field: FIQINDEX - FIQ index offset vector. */ |
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| 121 | #define TMS570_VIM_FIQINDEX_FIQINDEX(val) BSP_FLD32(val,0, 7) |
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| 122 | #define TMS570_VIM_FIQINDEX_FIQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7) |
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| 123 | #define TMS570_VIM_FIQINDEX_FIQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) |
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| 124 | |
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| 125 | |
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| 126 | /*----------------------TMS570_VIMFIRQPR----------------------*/ |
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| 127 | /* field: FIRQPRx - FIQ/IRQ program control bits. 96 bit register. 0-1 bits reserved. */ |
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| 128 | #define TMS570_VIM_FIRQPR_FIRQPRx(val) BSP_FLD32(val,0, 31) |
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| 129 | #define TMS570_VIM_FIRQPR_FIRQPRx_GET(reg) BSP_FLD32GET(reg,0, 31) |
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| 130 | #define TMS570_VIM_FIRQPR_FIRQPRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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| 131 | |
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| 132 | |
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| 133 | /*----------------------TMS570_VIMINTREQ----------------------*/ |
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| 134 | /* field: INTREQx - Pending interrupt bits. 96 bit register. */ |
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| 135 | #define TMS570_VIM_INTREQ_INTREQx(val) BSP_FLD32(val,0, 31) |
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| 136 | #define TMS570_VIM_INTREQ_INTREQx_GET(reg) BSP_FLD32GET(reg,0, 31) |
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| 137 | #define TMS570_VIM_INTREQ_INTREQx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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| 138 | |
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| 139 | |
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| 140 | /*--------------------TMS570_VIMREQENASET--------------------*/ |
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| 141 | /* field: REQENASETx - Request enable set bits. 96 bit register. 0-1 bits reserved. */ |
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| 142 | #define TMS570_VIM_REQENASET_REQENASETx(val) BSP_FLD32(val,0, 31) |
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| 143 | #define TMS570_VIM_REQENASET_REQENASETx_GET(reg) BSP_FLD32GET(reg,0, 31) |
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| 144 | #define TMS570_VIM_REQENASET_REQENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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| 145 | |
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| 146 | |
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| 147 | /*--------------------TMS570_VIMREQENACLR--------------------*/ |
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| 148 | /* field: REQENACLRx - Request enable clear bits. 96 bit register. 0-1 bits reserved. */ |
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| 149 | #define TMS570_VIM_REQENACLR_REQENACLRx(val) BSP_FLD32(val,0, 31) |
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| 150 | #define TMS570_VIM_REQENACLR_REQENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31) |
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| 151 | #define TMS570_VIM_REQENACLR_REQENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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| 152 | |
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| 153 | |
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| 154 | /*--------------------TMS570_VIMWAKEENASET--------------------*/ |
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| 155 | /* field: WAKEENASETx - Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled. */ |
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| 156 | #define TMS570_VIM_WAKEENASET_WAKEENASETx(val) BSP_FLD32(val,0, 31) |
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| 157 | #define TMS570_VIM_WAKEENASET_WAKEENASETx_GET(reg) BSP_FLD32GET(reg,0, 31) |
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| 158 | #define TMS570_VIM_WAKEENASET_WAKEENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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| 159 | |
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| 160 | |
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| 161 | /*--------------------TMS570_VIMWAKEENACLR--------------------*/ |
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| 162 | /* field: WAKEENACLRx - Wake-up enable clear bits. This vector determines whether the wake-up interrupt line is enabled. */ |
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| 163 | #define TMS570_VIM_WAKEENACLR_WAKEENACLRx(val) BSP_FLD32(val,0, 31) |
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| 164 | #define TMS570_VIM_WAKEENACLR_WAKEENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31) |
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| 165 | #define TMS570_VIM_WAKEENACLR_WAKEENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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| 166 | |
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| 167 | |
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| 168 | /*--------------------TMS570_VIMIRQVECREG--------------------*/ |
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| 169 | /* field: IRQVECREG - IRQ interrupt vector register. */ |
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| 170 | #define TMS570_VIM_IRQVECREG_IRQVECREG(val) BSP_FLD32(val,0, 31) |
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| 171 | #define TMS570_VIM_IRQVECREG_IRQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31) |
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| 172 | #define TMS570_VIM_IRQVECREG_IRQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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| 173 | |
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| 174 | |
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| 175 | /*--------------------TMS570_VIMFIQVECREG--------------------*/ |
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| 176 | /* field: FIQVECREG - FIQ interrupt vector register. */ |
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| 177 | #define TMS570_VIM_FIQVECREG_FIQVECREG(val) BSP_FLD32(val,0, 31) |
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| 178 | #define TMS570_VIM_FIQVECREG_FIQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31) |
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| 179 | #define TMS570_VIM_FIQVECREG_FIQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) |
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| 180 | |
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| 181 | |
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| 182 | /*----------------------TMS570_VIMCAPEVT----------------------*/ |
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| 183 | /* field: CAPEVTSRC1 - Capture event source 1 mapping control. */ |
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| 184 | #define TMS570_VIM_CAPEVT_CAPEVTSRC1(val) BSP_FLD32(val,16, 22) |
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| 185 | #define TMS570_VIM_CAPEVT_CAPEVTSRC1_GET(reg) BSP_FLD32GET(reg,16, 22) |
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| 186 | #define TMS570_VIM_CAPEVT_CAPEVTSRC1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22) |
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| 187 | |
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| 188 | /* field: CAPEVTSRC0 - the capture event source 0 of the RTI: */ |
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| 189 | #define TMS570_VIM_CAPEVT_CAPEVTSRC0(val) BSP_FLD32(val,0, 6) |
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| 190 | #define TMS570_VIM_CAPEVT_CAPEVTSRC0_GET(reg) BSP_FLD32GET(reg,0, 6) |
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| 191 | #define TMS570_VIM_CAPEVT_CAPEVTSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) |
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| 192 | |
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| 193 | |
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| 194 | /*---------------------TMS570_VIMCHANCTRL---------------------*/ |
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| 195 | /* field: CHANMAPx0 - CHANMAPx 0(6-0). Interrupt CHANx 0 mapping control. */ |
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| 196 | #define TMS570_VIM_CHANCTRL_CHANMAPx0(val) BSP_FLD32(val,24, 30) |
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| 197 | #define TMS570_VIM_CHANCTRL_CHANMAPx0_GET(reg) BSP_FLD32GET(reg,24, 30) |
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| 198 | #define TMS570_VIM_CHANCTRL_CHANMAPx0_SET(reg,val) BSP_FLD32SET(reg, val,24, 30) |
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| 199 | |
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| 200 | /* field: CHANMAPx1 - CHANMAPx 1(6-0). Interrupt CHANx 1 mapping control. */ |
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| 201 | #define TMS570_VIM_CHANCTRL_CHANMAPx1(val) BSP_FLD32(val,16, 22) |
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| 202 | #define TMS570_VIM_CHANCTRL_CHANMAPx1_GET(reg) BSP_FLD32GET(reg,16, 22) |
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| 203 | #define TMS570_VIM_CHANCTRL_CHANMAPx1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22) |
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| 204 | |
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| 205 | /* field: CHANMAPx2 - CHANMAPx 2(6-0). Interrupt CHANx 2 mapping control. */ |
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| 206 | #define TMS570_VIM_CHANCTRL_CHANMAPx2(val) BSP_FLD32(val,8, 14) |
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| 207 | #define TMS570_VIM_CHANCTRL_CHANMAPx2_GET(reg) BSP_FLD32GET(reg,8, 14) |
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| 208 | #define TMS570_VIM_CHANCTRL_CHANMAPx2_SET(reg,val) BSP_FLD32SET(reg, val,8, 14) |
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| 209 | |
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| 210 | /* field: CHANMAPx3 - CHANMAPx 3(6-0). Interrupt CHANx 3 mapping control. */ |
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| 211 | #define TMS570_VIM_CHANCTRL_CHANMAPx3(val) BSP_FLD32(val,0, 6) |
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| 212 | #define TMS570_VIM_CHANCTRL_CHANMAPx3_GET(reg) BSP_FLD32GET(reg,0, 6) |
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| 213 | #define TMS570_VIM_CHANCTRL_CHANMAPx3_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) |
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| 214 | |
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| 215 | |
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| 216 | |
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| 217 | #endif /* LIBBSP_ARM_tms570_VIM */ |
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