source: rtems/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys2.h @ bea49c9

4.11
Last change on this file since bea49c9 was bea49c9, checked in by Premysl Houdek <kom541000@…>, on Jul 16, 2015 at 2:26:09 PM

bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.

The header files are generated by script make_header.py.
Current script's version can be found at:

https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python

Registers offsets and fields have been extracted from reference manual.

Signed-off-by: Premysl Houdek <kom541000@…>

  • Property mode set to 100644
File size: 8.3 KB
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1/* The header file is generated by make_header.py from SYS2.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_tms570_SYS2
40#define LIBBSP_ARM_tms570_SYS2
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t PLLCTL3;           /*PLL Control Register 3*/
46  uint8_t reserved1 [4];
47  uint32_t STCCLKDIV;         /*CPU Logic BIST Clock Divider*/
48  uint8_t reserved2 [24];
49  uint32_t ECPCNTL;           /*ECP Control Register*/
50  uint8_t reserved3 [20];
51  uint32_t CLK2CNTRL;         /*Clock 2 Control Register*/
52  uint32_t VCLKACON1;         /*Peripheral Asynchronous Clock Configuration 1 Register*/
53  uint8_t reserved4 [44];
54  uint32_t CLKSLIP;           /*Clock Slip Register*/
55  uint8_t reserved5 [120];
56  uint32_t EFC_CTLREG;        /*EFUSE Controller Control Register*/
57  uint32_t DIEDL_REG0;        /*Die Identification Register*/
58  uint32_t DIEDH_REG1;        /*Die Identification Register*/
59  uint32_t DIEDL_REG2;        /*Die Identification Register*/
60  uint32_t DIEDH_REG3;        /*Die Identification Register*/
61} tms570_sys2_t;
62
63
64/*---------------------TMS570_SYS2PLLCTL3---------------------*/
65/* field: ODPLL2 - Internal PLL Output Divider */
66#define TMS570_SYS2_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
67#define TMS570_SYS2_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
68#define TMS570_SYS2_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31)
69
70/* field: PLLDIV2 - PLL2 Output Clock Divider */
71#define TMS570_SYS2_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28)
72#define TMS570_SYS2_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28)
73#define TMS570_SYS2_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
74
75/* field: REFCLKDIV2 - REFCLKDIV2 */
76#define TMS570_SYS2_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21)
77#define TMS570_SYS2_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21)
78#define TMS570_SYS2_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
79
80/* field: PLLMUL2 - PLL2 Multiplication Factor */
81#define TMS570_SYS2_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15)
82#define TMS570_SYS2_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15)
83#define TMS570_SYS2_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
84
85
86/*--------------------TMS570_SYS2STCCLKDIV--------------------*/
87/* field: CLKDIV - Clock divider/prescaler for CPU clock during logic BIST */
88#define TMS570_SYS2_STCCLKDIV_CLKDIV(val) BSP_FLD32(val,24, 26)
89#define TMS570_SYS2_STCCLKDIV_CLKDIV_GET(reg) BSP_FLD32GET(reg,24, 26)
90#define TMS570_SYS2_STCCLKDIV_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
91
92
93/*---------------------TMS570_SYS2ECPCNTL---------------------*/
94/* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */
95#define TMS570_SYS2_ECPCNTL_ECPSSEL BSP_FLD32(24)
96
97/* field: ECPCOS - ECP continue on suspend. */
98#define TMS570_SYS2_ECPCNTL_ECPCOS BSP_FLD32(23)
99
100/* field: ECPINSEL - Select ECP input clock source. */
101#define TMS570_SYS2_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17)
102#define TMS570_SYS2_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17)
103#define TMS570_SYS2_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17)
104
105/* field: ECPDIV - ECP divider value. */
106#define TMS570_SYS2_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15)
107#define TMS570_SYS2_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
108#define TMS570_SYS2_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
109
110
111/*--------------------TMS570_SYS2CLK2CNTRL--------------------*/
112/* field: VCLK3R - VBUS clock3 ratio. */
113#define TMS570_SYS2_CLK2CNTRL_VCLK3R(val) BSP_FLD32(val,0, 3)
114#define TMS570_SYS2_CLK2CNTRL_VCLK3R_GET(reg) BSP_FLD32GET(reg,0, 3)
115#define TMS570_SYS2_CLK2CNTRL_VCLK3R_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
116
117
118/*--------------------TMS570_SYS2VCLKACON1--------------------*/
119/* field: VCLKA4R - Clock divider for the VCLKA4 source. Output will be present on VCLKA4_DIVR. */
120#define TMS570_SYS2_VCLKACON1_VCLKA4R(val) BSP_FLD32(val,24, 26)
121#define TMS570_SYS2_VCLKACON1_VCLKA4R_GET(reg) BSP_FLD32GET(reg,24, 26)
122#define TMS570_SYS2_VCLKACON1_VCLKA4R_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
123
124/* field: VCLKA4_DIV_CDDIS - Disable the VCLKA4 divider output. */
125#define TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS BSP_FLD32(20)
126
127/* field: VCLKA4S - Peripheral asynchronous clock4 source. */
128#define TMS570_SYS2_VCLKACON1_VCLKA4S(val) BSP_FLD32(val,16, 19)
129#define TMS570_SYS2_VCLKACON1_VCLKA4S_GET(reg) BSP_FLD32GET(reg,16, 19)
130#define TMS570_SYS2_VCLKACON1_VCLKA4S_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
131
132/* field: VCLKA3R - Clock divider for the VCLKA3 source. Output will be present on VCLKA3_DIVR. */
133#define TMS570_SYS2_VCLKACON1_VCLKA3R(val) BSP_FLD32(val,8, 10)
134#define TMS570_SYS2_VCLKACON1_VCLKA3R_GET(reg) BSP_FLD32GET(reg,8, 10)
135#define TMS570_SYS2_VCLKACON1_VCLKA3R_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
136
137/* field: VCLKA3_DIV_CDDIS - Disable the VCLKA3 divider output. */
138#define TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS BSP_FLD32(4)
139
140/* field: VCLKA3S - Peripheral asynchronous clock3 source. */
141#define TMS570_SYS2_VCLKACON1_VCLKA3S(val) BSP_FLD32(val,0, 3)
142#define TMS570_SYS2_VCLKACON1_VCLKA3S_GET(reg) BSP_FLD32GET(reg,0, 3)
143#define TMS570_SYS2_VCLKACON1_VCLKA3S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
144
145
146/*---------------------TMS570_SYS2CLKSLIP---------------------*/
147/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
148#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
149#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
150#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
151
152/* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */
153#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3)
154#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
155#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
156
157
158/*-------------------TMS570_SYS2EFC_CTLREG-------------------*/
159/* field: EFC_INSTR_WEN - Enable user write of 4 EFUSE controller instructions. */
160#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN(val) BSP_FLD32(val,0, 3)
161#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_GET(reg) BSP_FLD32GET(reg,0, 3)
162#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
163
164
165/*-------------------TMS570_SYS2DIEDL_REG0-------------------*/
166/* field: DIE - This read-only register contains the lower/upper word (31:0) of the die ID information. */
167#define TMS570_SYS2_DIEDL_REG0_DIE(val) BSP_FLD32(val,0, 31)
168#define TMS570_SYS2_DIEDL_REG0_DIE_GET(reg) BSP_FLD32GET(reg,0, 31)
169#define TMS570_SYS2_DIEDL_REG0_DIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
170
171
172
173#endif /* LIBBSP_ARM_tms570_SYS2 */
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